40 lines
978 B
Systemverilog
40 lines
978 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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logic a, b;
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int n;
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// === Goto repetition [->N] error paths ===
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// Error: non-constant count
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assert property (@(posedge clk) a[->n] |-> b)
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else $error("FAIL");
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// Unsupported: zero count
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assert property (@(posedge clk) a[->0] |-> b)
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else $error("FAIL");
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// Error: negative count
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assert property (@(posedge clk) a[->-1] |-> b)
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else $error("FAIL");
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// === Nonconsecutive repetition [=N] error paths ===
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// Error: non-constant count
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assert property (@(posedge clk) a[=n] |-> b)
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else $error("FAIL");
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// Unsupported: zero count
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assert property (@(posedge clk) a[=0] |-> b)
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else $error("FAIL");
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// Error: negative count
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assert property (@(posedge clk) a[=-1] |-> b)
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else $error("FAIL");
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endmodule
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