47 lines
990 B
Systemverilog
47 lines
990 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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logic rst_n = 0;
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logic en = 0;
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logic q = 0;
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logic [7:0] cnt = 0;
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// Synchronous active-low reset driving runtime-varying signals, so the
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// asserted and covered properties are not constant-folded away.
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always_ff @(posedge clk) begin
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rst_n <= (cyc >= 2);
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en <= cyc[0];
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if (!rst_n) begin
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q <= 1'b0;
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cnt <= '0;
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end
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else if (en) begin
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q <= ~q;
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cnt <= cnt + 8'd1;
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end
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end
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a :
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assert property (@(posedge clk) !rst_n |=> q == 1'b0);
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c :
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cover property (@(posedge clk) disable iff (!rst_n) en && cnt == $past(cnt));
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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