27 lines
695 B
Systemverilog
27 lines
695 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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logic a;
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int n;
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// Bad: non-constant repetition count
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assert property (@(posedge clk) a [*n] |-> 1);
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// Bad: [*0] unsupported exact zero repetition
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assert property (@(posedge clk) a [*0] |-> 1);
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// Bad: max count < min count
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assert property (@(posedge clk) a [*3:1] |-> 1);
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// Bad: non-constant max count
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assert property (@(posedge clk) a [*1:n] |-> 1);
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// Bad: [*N:0] zero max count
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assert property (@(posedge clk) a [*0:0] |-> 1);
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endmodule
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