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574c69c092
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574c69c092 | |
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e2f5854088 |
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@ -105,6 +105,7 @@ Jamey Hicks
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Jamie Iles
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Jan Van Winkel
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Jean Berniolles
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Jens Yuechao Liu
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Jeremy Bennett
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Jesse Taube
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Jevin Sweval
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@ -719,6 +719,11 @@ Summary:
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automatically. Variables explicitly annotated with
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:option:`/*verilator&32;split_var*/` are still split.
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.. option:: --fslice-element-limit
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Rarely needed. Set the maximum array size (number of elements)
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for slice optimization to avoid excessive memory usage.
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.. option:: -future0 <option>
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Rarely needed. Suppress an unknown Verilator option for an option that
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@ -1458,13 +1458,16 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
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DECL_OPTION("-freloop", FOnOff, &m_fReloop);
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DECL_OPTION("-freorder", FOnOff, &m_fReorder);
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DECL_OPTION("-fslice", FOnOff, &m_fSlice);
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DECL_OPTION("-fslice-element-limit", CbVal, [this, fl](const char* valp) {
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m_fSliceElementLimit = std::atoi(valp);
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if (m_fSliceElementLimit < 0) fl->v3fatal("--fslice-element-limit must be >= 0: " << valp);
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});
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DECL_OPTION("-fsplit", FOnOff, &m_fSplit);
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DECL_OPTION("-fsubst", FOnOff, &m_fSubst);
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DECL_OPTION("-fsubst-const", FOnOff, &m_fSubstConst);
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DECL_OPTION("-ftable", FOnOff, &m_fTable);
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DECL_OPTION("-ftaskify-all-forked", FOnOff, &m_fTaskifyAll).undocumented(); // Debug
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DECL_OPTION("-fvar-split", FOnOff, &m_fVarSplit);
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DECL_OPTION("-G", CbPartialMatch, [this](const char* optp) { addParameter(optp, false); });
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DECL_OPTION("-gate-stmts", Set, &m_gateStmts);
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DECL_OPTION("-gdb", CbCall, []() {}); // Processed only in bin/verilator shell
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@ -413,6 +413,7 @@ private:
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bool m_fReloop; // main switch: -fno-reloop: reform loops
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bool m_fReorder; // main switch: -fno-reorder: reorder assignments in blocks
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bool m_fSlice = true; // main switch: -fno-slice: array assignment slicing
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int m_fSliceElementLimit = 256; // main switch: --fslice-element-limit
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bool m_fSplit; // main switch: -fno-split: always assignment splitting
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bool m_fSubst; // main switch: -fno-subst: substitute expression temp values
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bool m_fSubstConst; // main switch: -fno-subst-const: final constant substitution
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@ -726,6 +727,7 @@ public:
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bool fReloop() const { return m_fReloop; }
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bool fReorder() const { return m_fReorder; }
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bool fSlice() const { return m_fSlice; }
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int fSliceElementLimit() const { return m_fSliceElementLimit; }
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bool fSplit() const { return m_fSplit; }
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bool fSubst() const { return m_fSubst; }
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bool fSubstConst() const { return m_fSubstConst; }
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@ -58,6 +58,7 @@ class SliceVisitor final : public VNVisitor {
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// STATE - across all visitors
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VDouble0 m_statAssigns; // Statistic tracking
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VDouble0 m_statSliceElementSkips; // Statistic tracking
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// STATE - for current visit position (use VL_RESTORER)
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AstNode* m_assignp = nullptr; // Assignment we are under
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@ -248,6 +249,14 @@ class SliceVisitor final : public VNVisitor {
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return false;
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}
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// Skip optimization if array is too large
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const int elements = arrayp->rangep()->elementsConst();
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const int elementLimit = v3Global.opt.fSliceElementLimit();
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if (elements > elementLimit && elementLimit > 0) {
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++m_statSliceElementSkips;
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return false;
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}
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UINFO(4, "Slice optimizing " << nodep);
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++m_statAssigns;
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@ -256,7 +265,6 @@ class SliceVisitor final : public VNVisitor {
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// Assign of an ascending range slice to a descending range one must reverse
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// the elements
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AstNodeAssign* newlistp = nullptr;
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const int elements = arrayp->rangep()->elementsConst();
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for (int elemIdx = 0; elemIdx < elements; ++elemIdx) {
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// Original node is replaced, so it is safe to copy it one time even if it is impure.
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AstNodeAssign* const newp
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@ -383,6 +391,8 @@ public:
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explicit SliceVisitor(AstNetlist* nodep) { iterate(nodep); }
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~SliceVisitor() override {
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V3Stats::addStat("Optimizations, Slice array assignments", m_statAssigns);
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V3Stats::addStat("Optimizations, Slice array skips due to size limit",
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m_statSliceElementSkips);
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}
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};
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@ -0,0 +1,20 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_opt_slice_element_limit.v"
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test.compile(verilator_flags2=['--stats', '--fslice-element-limit', '10'])
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test.file_grep(test.stats, r'Optimizations, Slice array skips due to size limit\s+(\d+)', 4)
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test.passes()
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@ -0,0 +1,20 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic [7:0] i1 [8],
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input logic [7:0] i2 [16],
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input logic [7:0] i3 [512],
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output logic [7:0] o1 [8],
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output logic [7:0] o2 [16],
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output logic [7:0] o3 [256]
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,20 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_opt_slice_element_limit.v"
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test.compile(verilator_flags2=['--stats', '--fslice-element-limit', '0'])
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test.file_grep(test.stats, r'Optimizations, Slice array skips due to size limit\s+(\d+)', 0)
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test.passes()
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@ -0,0 +1,2 @@
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%Error: --fslice-element-limit must be >= 0: -100
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... See the manual at https://verilator.org/verilator_doc.html?v=5.043 for more assistance.
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.top_filename = "t/t_opt_slice_element_limit.v"
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test.golden_filename = "t/t_opt_slice_element_limit_bad.out"
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test.lint(fails=True,
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verilator_flags2=['--stats', '--fslice-element-limit', '-100'],
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except_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,20 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_opt_slice_element_limit.v"
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test.compile(verilator_flags2=['--stats'])
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test.file_grep(test.stats, r'Optimizations, Slice array skips due to size limit\s+(\d+)', 1)
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test.passes()
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