Change error messages to more often suggest documentation

Changes

@@ -23,6 +23,7 @@ Verilator 5.035 devel
 * Support command-line overriding `define (#5900) (#5908). [Brian Li]
 * Support `$setuphold` (#5884). [Krzysztof Sychla]
 * Support `systemc_interface and related inside `class`.
+* Change `--trace` to `--trace-vcd`.
 * Add multi-thread hierarchical simulation (#2583) (#5871). [Bartłomiej Chmiel, Antmicro Ltd.]
 * Add check for `let` misused in statement context (#5733).
 * Add used language to `--preproc-resolve` output (#5795). [Kamil Rakoczy, Antmicro Ltd.]

bin/verilator

@@ -473,7 +473,7 @@ detailed descriptions of these arguments.
     --timescale-override <timescale>  Overrides all timescales
     --top <topname>             Alias of --top-module
     --top-module <topname>      Name of top-level input module
-    --trace                     Enable waveform creation
+    --trace                     Enable VCD waveform creation
     --trace-coverage            Enable tracing of coverage
     --trace-depth <levels>      Depth of tracing
     --trace-fst                 Enable FST waveform creation
@@ -483,6 +483,7 @@ detailed descriptions of these arguments.
     --trace-saif                Enable SAIF file creation
     --trace-structs             Enable tracing structure names
     --trace-threads <threads>   Enable FST waveform creation on separate threads
+    --trace-vcd                 Enable VCD waveform creation
     --no-trace-top              Do not emit traces for signals in the top module generated by verilator
     --trace-underscore          Enable tracing of _signals
      -U<var>                    Undefine preprocessor define

docs/guide/exe_verilator.rst

@@ -1493,7 +1493,7 @@ Summary:
    but may run in a multithreaded environment. With "--threads N",
    where N >= 2, the model is generated to run multithreaded on up to N
    threads. See :ref:`Multithreading`. This option also applies to
-   :vlopt:`--trace` (but not :vlopt:`--trace-fst`).
+   :vlopt:`--trace-vcd` (but not :vlopt:`--trace-fst`).
 
 .. option:: --no-threads
 
@@ -1574,26 +1574,19 @@ Summary:
 
 .. option:: --trace
 
-   Adds waveform tracing code to the model using VCD format. This overrides
-   :vlopt:`--trace-fst`.
+   Deprecated; use :vlopt:`--trace-fst`, :vlopt:`--trace-saif` or
+   :vlopt:`--trace-vcd` instead.
 
-   Verilator will generate additional :file:`<prefix>__Trace*.cpp` files
-   must be compiled.  In addition :file:`verilated_vcd_sc.cpp`
-   (for SystemC traces) or :file:`verilated_vcd_c.cpp` (for both) must be
-   compiled and linked in.  If using the Verilator-generated Makefiles,
-   these files will be added to the source file lists for you.  If you are
-   not using the Verilator Makefiles, you will need to add these to your
-   Makefile manually.
+   Using :vlopt:`--trace` without :vlopt:`--trace-fst` nor
+   :vlopt:`--trace-fst` requests VCD traces.
 
-   Having tracing compiled in may result in small performance losses,
-   even when tracing is not turned on during model execution.
+   Using :vlopt:`--trace` :vlopt:`--trace-fst` requests FST traces.
 
-   When using :vlopt:`--threads`, VCD tracing is parallelized, using the
-   same number of threads as passed to :vlopt:`--threads`.
+   Using :vlopt:`--trace` :vlopt:`--trace-saif` requests SAIF traces.
 
 .. option:: --trace-coverage
 
-   With :vlopt:`--trace` and ``--coverage-*``, enable tracing to include a
+   With `--trace-*`  and ``--coverage-*``, enable tracing to include a
    traced signal for every :vlopt:`--coverage-line` or
    :vlopt:`--coverage-user`\ -inserted coverage point, to assist in
    debugging coverage items.  Note :vlopt:`--coverage-toggle` does not get
@@ -1673,6 +1666,24 @@ Summary:
    underscore. Otherwise, these signals are not output during tracing.  See
    also :vlopt:`--coverage-underscore` option.
 
+.. option:: --trace-vcd
+
+   Adds waveform tracing code to the model using VCD format.
+
+   Verilator will generate additional :file:`<prefix>__Trace*.cpp` files
+   must be compiled.  In addition :file:`verilated_vcd_sc.cpp`
+   (for SystemC traces) or :file:`verilated_vcd_c.cpp` (for both) must be
+   compiled and linked in.  If using the Verilator-generated Makefiles,
+   these files will be added to the source file lists for you.  If you are
+   not using the Verilator Makefiles, you will need to add these to your
+   Makefile manually.
+
+   Having tracing compiled in may result in small performance losses,
+   even when tracing is not turned on during model execution.
+
+   When using :vlopt:`--threads`, VCD tracing is parallelized, using the
+   same number of threads as passed to :vlopt:`--threads`.
+
 .. option:: -U<var>
 
    Undefines the given preprocessor symbol.

docs/guide/extensions.rst

@@ -619,7 +619,7 @@ or "`ifdef`"'s may break other tools.
    Attached to a DPI import to indicate that function should be called when
    initializing tracing. This attribute is indented only to be used
    internally in code that Verilator generates when :vlopt:`--lib-create`
-   or :vlopt:`--hierarchical` is used along with :vlopt:`--trace`.
+   or :vlopt:`--hierarchical` is used along with :vlopt:`--trace-vcd`.
 
 .. option:: /*verilator&32;tracing_off*/
 

docs/guide/faq.rst

@@ -128,7 +128,7 @@ How do I generate waveforms (traces) in C++?
 
 See also the next question for tracing in SystemC mode.
 
-A. Pass the :vlopt:`--trace` option to Verilator.  Then you may use ``$dumpfile`` and
+A. Pass the :vlopt:`--trace-vcd` option to Verilator.  Then you may use ``$dumpfile`` and
    ``$dumpvars`` to enable traces, the same as with any Verilog simulator,
    although Verilator ignores the arguments to ``$dumpvars``. See
    ``examples/make_tracing_c`` in the distribution.
@@ -177,7 +177,7 @@ file.
 How do I generate waveforms (traces) in SystemC?
 """"""""""""""""""""""""""""""""""""""""""""""""
 
-A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level
+A. Pass the :vlopt:`--trace-vcd` option to Verilator, and in your top-level
    :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`.  Then you
    may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as
    with any Verilog simulator; see the non-SystemC example in

docs/guide/files.rst

@@ -65,9 +65,9 @@ For --cc/--sc, it creates:
    * - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
      - Infrequent cold routines (hashed to reduce build times)
    * - *{prefix}*\ ___024root__Trace\ *{__n}*\ .cpp
-     - Wave file generation code (from --trace)
+     - Wave file generation code (from --trace-*)
    * - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*\ .cpp
-     - Wave file generation code (from --trace)
+     - Wave file generation code (from --trace-*)
    * - *{prefix}*\ __Dpi.h
      - DPI import and export declarations (from --dpi)
    * - *{prefix}*\ __Dpi.cpp

docs/guide/languages.rst

@@ -488,7 +488,7 @@ $bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed,
 
 $dump/$dumpports and related
   $dumpfile or $dumpports will create a VCD or FST file (based on
-  the :vlopt:`--trace` option given when the model was Verilated). This
+  the :vlopt:`--trace-vcd` option given when the model was Verilated). This
   will take effect starting at the next eval() call.  If you have multiple
   Verilated designs under the same C model, this will dump signals
   only from the design containing the $dumpvars.

docs/guide/verilating.rst

@@ -221,7 +221,7 @@ model, it may be beneficial to performance to adjust the
 influences the partitioning of the model by adjusting the assumed execution
 time of DPI imports.
 
-When using :vlopt:`--trace` to perform VCD tracing, the VCD trace
+When using :vlopt:`--trace-vcd` to perform VCD tracing, the VCD trace
 construction is parallelized using the same number of threads as specified
 with :vlopt:`--threads`, and is executed on the same thread pool as the model.
 
@@ -293,8 +293,8 @@ and must be called only by the eval thread.
 If using :vlopt:`--sc`, the SystemC kernel is not thread-safe; therefore,
 the eval thread and main thread must be the same.
 
-If using :vlopt:`--trace`, the tracing classes must be constructed and
-called from the main thread.
+If using :vlopt:`--trace-vcd` or other trace options, the tracing classes
+must be constructed and called from the main thread.
 
 If using :vlopt:`--vpi`, since SystemVerilog VPI was not architected by
 IEEE to be multithreaded, Verilator requires all VPI calls are only made
@@ -457,8 +457,7 @@ SystemC include directories and link to the SystemC libraries.
 
 .. describe:: TRACE
 
-   Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS
-   --trace".
+   Deprecated. Same as TRACE_VCD, which should be used instead.
 
 .. describe:: TRACE_FST
 
@@ -470,6 +469,11 @@ SystemC include directories and link to the SystemC libraries.
    Optional. Enables SAIF tracing if present, equivalent to "VERILATOR_ARGS
    --trace-saif".
 
+.. describe:: TRACE_VCD
+
+   Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS
+   --trace-vcd".
+
 .. describe:: VERILATOR_ARGS
 
    Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir`

examples/make_protect_lib/Makefile

@@ -43,7 +43,7 @@ VERILATOR_FLAGS += -Wall
 VERILATOR_FLAGS += -CFLAGS -DVL_TIME_CONTEXT
 
 # Make waveforms
-TOP_VERILATOR_FLAGS = $(VERILATOR_FLAGS) --trace
+TOP_VERILATOR_FLAGS = $(VERILATOR_FLAGS) --trace-vcd
 
 ######################################################################
 default: run

examples/make_tracing_c/Makefile

@@ -40,7 +40,7 @@ VERILATOR_FLAGS += -x-assign fast
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms
-VERILATOR_FLAGS += --trace
+VERILATOR_FLAGS += --trace-vcd
 # Check SystemVerilog assertions
 VERILATOR_FLAGS += --assert
 # Generate coverage analysis

examples/make_tracing_sc/Makefile

@@ -41,7 +41,7 @@ VERILATOR_FLAGS += -x-assign fast
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms
-VERILATOR_FLAGS += --trace
+VERILATOR_FLAGS += --trace-vcd
 # Check SystemVerilog assertions
 VERILATOR_FLAGS += --assert
 # Generate coverage analysis

include/verilated.cpp

@@ -3038,7 +3038,7 @@ void VerilatedContext::trace(VerilatedTraceBaseC* tfp, int levels, int options)
     if (m_ns.m_traceBaseModelCbs.empty())
         VL_FATAL_MT("", 0, "",
                     "Testbench C call to 'VerilatedContext::trace()' requires model(s) Verilated"
-                    " with --trace or --trace-vcd option");
+                    " with --trace-fst or --trace-vcd option");
     for (auto& cbr : m_ns.m_traceBaseModelCbs) cbr(tfp, levels, options);
 }
 void VerilatedContext::traceBaseModelCbAdd(traceBaseModelCb_t cb) VL_MT_SAFE {

include/verilated_fst_c.cpp

@@ -101,6 +101,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
 void VerilatedFst::close() VL_MT_SAFE_EXCLUDES(m_mutex) {
     const VerilatedLockGuard lock{m_mutex};
     Super::closeBase();
+    emitTimeChangeMaybe();
     fstWriterClose(m_fst);
     m_fst = nullptr;
 }
@@ -108,10 +109,22 @@ void VerilatedFst::close() VL_MT_SAFE_EXCLUDES(m_mutex) {
 void VerilatedFst::flush() VL_MT_SAFE_EXCLUDES(m_mutex) {
     const VerilatedLockGuard lock{m_mutex};
     Super::flushBase();
+    emitTimeChangeMaybe();
     fstWriterFlushContext(m_fst);
 }
 
-void VerilatedFst::emitTimeChange(uint64_t timeui) { fstWriterEmitTimeChange(m_fst, timeui); }
+void VerilatedFst::emitTimeChange(uint64_t timeui) {
+    if (!timeui) fstWriterEmitTimeChange(m_fst, timeui);
+    m_timeui = timeui;
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedFst::emitTimeChangeMaybe() {
+    if (VL_UNLIKELY(m_timeui)) {
+        fstWriterEmitTimeChange(m_fst, m_timeui);
+        m_timeui = 0;
+    }
+}
 
 //=============================================================================
 // Decl
@@ -311,12 +324,14 @@ void VerilatedFst::configure(const VerilatedTraceConfig& config) {
 VL_ATTR_ALWINLINE
 void VerilatedFstBuffer::emitEvent(uint32_t code) {
     VL_DEBUG_IFDEF(assert(m_symbolp[code]););
+    m_owner.emitTimeChangeMaybe();
     fstWriterEmitValueChange(m_fst, m_symbolp[code], "1");
 }
 
 VL_ATTR_ALWINLINE
 void VerilatedFstBuffer::emitBit(uint32_t code, CData newval) {
     VL_DEBUG_IFDEF(assert(m_symbolp[code]););
+    m_owner.emitTimeChangeMaybe();
     fstWriterEmitValueChange(m_fst, m_symbolp[code], newval ? "1" : "0");
 }
 
@@ -325,6 +340,7 @@ void VerilatedFstBuffer::emitCData(uint32_t code, CData newval, int bits) {
     char buf[VL_BYTESIZE];
     VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtCDataToStr(buf, newval << (VL_BYTESIZE - bits));
+    m_owner.emitTimeChangeMaybe();
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
@@ -333,6 +349,7 @@ void VerilatedFstBuffer::emitSData(uint32_t code, SData newval, int bits) {
     char buf[VL_SHORTSIZE];
     VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtSDataToStr(buf, newval << (VL_SHORTSIZE - bits));
+    m_owner.emitTimeChangeMaybe();
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
@@ -341,6 +358,7 @@ void VerilatedFstBuffer::emitIData(uint32_t code, IData newval, int bits) {
     char buf[VL_IDATASIZE];
     VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtIDataToStr(buf, newval << (VL_IDATASIZE - bits));
+    m_owner.emitTimeChangeMaybe();
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
@@ -349,6 +367,7 @@ void VerilatedFstBuffer::emitQData(uint32_t code, QData newval, int bits) {
     char buf[VL_QUADSIZE];
     VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtQDataToStr(buf, newval << (VL_QUADSIZE - bits));
+    m_owner.emitTimeChangeMaybe();
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
@@ -365,10 +384,12 @@ void VerilatedFstBuffer::emitWData(uint32_t code, const WData* newvalp, int bits
         cvtEDataToStr(wp, newvalp[--words]);
         wp += VL_EDATASIZE;
     }
+    m_owner.emitTimeChangeMaybe();
     fstWriterEmitValueChange(m_fst, m_symbolp[code], m_strbufp);
 }
 
 VL_ATTR_ALWINLINE
 void VerilatedFstBuffer::emitDouble(uint32_t code, double newval) {
+    m_owner.emitTimeChangeMaybe();
     fstWriterEmitValueChange(m_fst, m_symbolp[code], &newval);
 }

include/verilated_fst_c.h

@@ -56,6 +56,7 @@ private:
     std::map<int, vlFstEnumHandle> m_local2fstdtype;
     vlFstHandle* m_symbolp = nullptr;  // same as m_code2symbol, but as an array
     char* m_strbufp = nullptr;  // String buffer long enough to hold maxBits() chars
+    uint64_t m_timeui = 0;  // Time to emit, 0 = not needed
 
     bool m_useFstWriterThread = false;  // Whether to use the separate FST writer thread
 
@@ -75,6 +76,7 @@ protected:
 
     // Called when the trace moves forward to a new time point
     void emitTimeChange(uint64_t timeui) override;
+    void emitTimeChangeMaybe();
 
     // Hooks called from VerilatedTrace
     bool preFullDump() override { return isOpen(); }

include/verilated_saif_c.cpp

@@ -15,9 +15,9 @@
 /// \brief Verilated C++ tracing in SAIF format implementation code
 ///
 /// This file must be compiled and linked against all Verilated objects
-/// that use --trace.
+/// that use --trace-saif.
 ///
-/// Use "verilator --trace" to add this to the Makefile for the linker.
+/// Use "verilator --trace-saif" to add this to the Makefile for the linker.
 ///
 //=============================================================================
 
@@ -319,6 +319,7 @@ void VerilatedSaif::close() VL_MT_SAFE_EXCLUDES(m_mutex) {
     finalizeSaifFileContents();
     clearCurrentlyCollectedData();
 
+    writeBuffered(true);
     ::close(m_filep);
     m_isOpen = false;
 
@@ -437,9 +438,25 @@ void VerilatedSaif::clearCurrentlyCollectedData() {
     m_activityAccumulators.clear();
 }
 
-void VerilatedSaif::printStr(const char* str) { ::write(m_filep, str, strlen(str)); }
+void VerilatedSaif::printStr(const char* str) {
+    m_buffer.append(str);
+    writeBuffered(false);
+}
 
-void VerilatedSaif::printStr(const std::string& str) { ::write(m_filep, str.c_str(), str.size()); }
+void VerilatedSaif::printStr(const std::string& str) {
+    m_buffer.append(str);
+    writeBuffered(false);
+}
+
+void VerilatedSaif::writeBuffered(bool force) {
+    if (VL_UNLIKELY(m_buffer.size() >= WRITE_BUFFER_SIZE || force)) {
+        if (VL_UNLIKELY(!m_buffer.empty())) {
+            ::write(m_filep, m_buffer.data(), m_buffer.size());
+            m_buffer = "";
+            m_buffer.reserve(WRITE_BUFFER_SIZE * 2);
+        }
+    }
+}
 
 //=============================================================================
 // Definitions
@@ -454,7 +471,7 @@ void VerilatedSaif::incrementIndent() { m_indent += 1; }
 void VerilatedSaif::decrementIndent() { m_indent -= 1; }
 
 void VerilatedSaif::printIndent() {
-    for (int i = 0; i < m_indent; ++i) printStr(" ");
+    printStr(std::string(m_indent, ' '));  // Must use () constructor
 }
 
 void VerilatedSaif::pushPrefix(const std::string& name, VerilatedTracePrefixType type) {

include/verilated_saif_c.h

@@ -52,8 +52,10 @@ private:
     int m_filep = 0;  // File we're writing to
     bool m_isOpen = false;  // True indicates open file
     std::string m_filename;  // Filename we're writing to (if open)
+    std::string m_buffer;  // Write data buffer
 
     int m_indent = 0;  // Indentation size in spaces
+    static constexpr size_t WRITE_BUFFER_SIZE = 256 * 1024;  // Bytes between write calls
 
     // Currently active scope
     VerilatedSaifActivityScope* m_currentScope = nullptr;
@@ -92,6 +94,7 @@ private:
 
     void printStr(const char* str);
     void printStr(const std::string& str);
+    void writeBuffered(bool force);
 
     void clearCurrentlyCollectedData();
 

include/verilated_vcd_c.cpp

@@ -15,9 +15,9 @@
 /// \brief Verilated C++ tracing in VCD format implementation code
 ///
 /// This file must be compiled and linked against all Verilated objects
-/// that use --trace.
+/// that use --trace-vcd.
 ///
-/// Use "verilator --trace" to add this to the Makefile for the linker.
+/// Use "verilator --trace-vcd" to add this to the Makefile for the linker.
 ///
 //=============================================================================
 
@@ -100,6 +100,8 @@ VerilatedVcd::VerilatedVcd(VerilatedVcdFile* filep) {
     m_wrBufp = new char[m_wrChunkSize * 8];
     m_wrFlushp = m_wrBufp + m_wrChunkSize * 6;
     m_writep = m_wrBufp;
+    m_wrTimeBeginp = nullptr;
+    m_wrTimeEndp = nullptr;
 }
 
 void VerilatedVcd::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
@@ -187,10 +189,19 @@ bool VerilatedVcd::preChangeDump() {
 }
 
 void VerilatedVcd::emitTimeChange(uint64_t timeui) {
-    printStr("#");
-    const std::string str = std::to_string(timeui);
-    printStr(str.c_str());
-    printStr("\n");
+    // Remember pointers when last emitted time stamp; if last output was
+    // timestamp backup and overwrite it.
+    // This is faster then checking on every signal change if time needs to
+    // be emitted.  Note buffer flushes may still emit a rare duplicate.
+    if (m_wrTimeEndp == m_writep) m_writep = m_wrTimeBeginp;
+    m_wrTimeBeginp = m_writep;
+    {
+        printStr("#");
+        const std::string str = std::to_string(timeui);
+        printStr(str.c_str());
+        printStr("\n");
+    }
+    m_wrTimeEndp = m_writep;
 }
 
 VerilatedVcd::~VerilatedVcd() {
@@ -257,6 +268,10 @@ void VerilatedVcd::bufferResize(size_t minsize) {
         m_wrBufp = new char[m_wrChunkSize * 8];
         std::memcpy(m_wrBufp, oldbufp, m_writep - oldbufp);
         m_writep = m_wrBufp + (m_writep - oldbufp);
+        if (m_wrTimeBeginp) {
+            m_wrTimeBeginp = m_wrBufp + (m_wrTimeBeginp - oldbufp);
+            m_wrTimeEndp = m_wrBufp + (m_wrTimeEndp - oldbufp);
+        }
         m_wrFlushp = m_wrBufp + m_wrChunkSize * 6;
         VL_DO_CLEAR(delete[] oldbufp, oldbufp = nullptr);
     }
@@ -293,6 +308,8 @@ void VerilatedVcd::bufferFlush() VL_MT_UNSAFE_ONE {
 
     // Reset buffer
     m_writep = m_wrBufp;
+    m_wrTimeBeginp = nullptr;
+    m_wrTimeEndp = nullptr;
 }
 
 //=============================================================================

include/verilated_vcd_c.h

@@ -55,6 +55,8 @@ private:
     char* m_wrBufp;  // Output buffer
     char* m_wrFlushp;  // Output buffer flush trigger location
     char* m_writep;  // Write pointer into output buffer
+    char* m_wrTimeBeginp = nullptr;  // Write pointer for last time dump
+    char* m_wrTimeEndp = nullptr;  // Write pointer for last time dump
     size_t m_wrChunkSize;  // Output buffer size
     size_t m_maxSignalBytes = 0;  // Upper bound on number of bytes a single signal can generate
     uint64_t m_wroteBytes = 0;  // Number of bytes written to this file

src/V3EmitCMake.cpp

@@ -110,15 +110,15 @@ class CMakeEmitter final {
         cmake_set_raw(*of, name + "_TIMING", v3Global.usesTiming() ? "1" : "0");
         *of << "# Threaded output mode?  1/N threads (from --threads)\n";
         cmake_set_raw(*of, name + "_THREADS", cvtToStr(v3Global.opt.threads()));
-        *of << "# VCD Tracing output mode?  0/1 (from --trace)\n";
-        cmake_set_raw(*of, name + "_TRACE_VCD",
-                      (v3Global.opt.trace() && v3Global.opt.traceFormat().vcd()) ? "1" : "0");
         *of << "# FST Tracing output mode? 0/1 (from --trace-fst)\n";
         cmake_set_raw(*of, name + "_TRACE_FST",
                       (v3Global.opt.trace() && v3Global.opt.traceFormat().fst()) ? "1" : "0");
         *of << "# SAIF Tracing output mode? 0/1 (from --trace-saif)\n";
         cmake_set_raw(*of, name + "_TRACE_SAIF",
                       (v3Global.opt.trace() && v3Global.opt.traceFormat().saif()) ? "1" : "0");
+        *of << "# VCD Tracing output mode?  0/1 (from --trace-vcd)\n";
+        cmake_set_raw(*of, name + "_TRACE_VCD",
+                      (v3Global.opt.trace() && v3Global.opt.traceFormat().vcd()) ? "1" : "0");
 
         *of << "\n### Sources...\n";
         std::vector<string> classes_fast;

src/V3EmitCModel.cpp

@@ -584,7 +584,7 @@ class EmitCModel final : public EmitCFunc {
         puts(/****/ "vl_fatal(__FILE__, __LINE__, __FILE__,\"'" + topClassName()
              + "::trace()' called on non-" + v3Global.opt.traceClassBase() + "C object;\"\n"
              + "\" use --trace-fst with VerilatedFst object,"
-             + " and --trace with VerilatedVcd object\");\n");
+             + " and --trace-vcd with VerilatedVcd object\");\n");
         puts(/**/ "}\n");
         puts(/**/ "stfp->spTrace()->addModel(this);\n");
         puts(/**/ "stfp->spTrace()->addInitCb(&" + protect("trace_init")

src/V3EmitMk.cpp

@@ -551,14 +551,10 @@ public:
         of.puts("VM_PARALLEL_BUILDS = ");
         of.puts(v3Global.useParallelBuild() ? "1" : "0");
         of.puts("\n");
-        of.puts("# Tracing output mode?  0/1 (from --trace/--trace-fst/--trace-saif)\n");
+        of.puts("# Tracing output mode?  0/1 (from --trace-fst/--trace-saif/--trace-vcd)\n");
         of.puts("VM_TRACE = ");
         of.puts(v3Global.opt.trace() ? "1" : "0");
         of.puts("\n");
-        of.puts("# Tracing output mode in VCD format?  0/1 (from --trace)\n");
-        of.puts("VM_TRACE_VCD = ");
-        of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().vcd() ? "1" : "0");
-        of.puts("\n");
         of.puts("# Tracing output mode in FST format?  0/1 (from --trace-fst)\n");
         of.puts("VM_TRACE_FST = ");
         of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().fst() ? "1" : "0");
@@ -567,6 +563,10 @@ public:
         of.puts("VM_TRACE_SAIF = ");
         of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().saif() ? "1" : "0");
         of.puts("\n");
+        of.puts("# Tracing output mode in VCD format?  0/1 (from --trace-vcd)\n");
+        of.puts("VM_TRACE_VCD = ");
+        of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().vcd() ? "1" : "0");
+        of.puts("\n");
 
         of.puts("\n### Object file lists...\n");
         for (int support = 0; support < 3; ++support) {

src/V3Error.cpp

@@ -72,7 +72,7 @@ string V3ErrorGuarded::msgPrefix() VL_REQUIRES(m_mutex) {
         return "-Info: ";
     } else if (code == V3ErrorCode::EC_FATAL) {
         return "%Error: ";
-    } else if (code == V3ErrorCode::EC_FATALEXIT) {
+    } else if (code == V3ErrorCode::EC_FATALMANY) {
         return "%Error: ";
     } else if (code == V3ErrorCode::EC_FATALSRC) {
         return "%Error: Internal Error: ";
@@ -162,7 +162,7 @@ void V3ErrorGuarded::v3errorEnd(std::ostringstream& sstr, const string& extra)
     // Output
     if (
 #ifndef V3ERROR_NO_GLOBAL_
-        !(v3Global.opt.quietExit() && m_errorCode == V3ErrorCode::EC_FATALEXIT)
+        !(v3Global.opt.quietExit() && m_errorCode == V3ErrorCode::EC_FATALMANY)
 #else
         true
 #endif
@@ -172,54 +172,54 @@ void V3ErrorGuarded::v3errorEnd(std::ostringstream& sstr, const string& extra)
     if (!m_errorSuppressed
         && !(m_errorCode == V3ErrorCode::EC_INFO || m_errorCode == V3ErrorCode::USERINFO)) {
         const bool anError = isError(m_errorCode, m_errorSuppressed);
-        if (m_errorCode >= V3ErrorCode::EC_FIRST_NAMED && !m_describedWeb) {
-            m_describedWeb = true;
-            std::cerr << warnMore() << "... For " << (anError ? "error" : "warning")
-                      << " description see https://verilator.org/warn/" << m_errorCode.ascii()
-                      << "?v=" << PACKAGE_VERSION_NUMBER_STRING << endl;
-        }
-        if (!m_describedEachWarn[m_errorCode] && !m_pretendError[m_errorCode]) {
+        if (m_errorCode != V3ErrorCode::EC_FATALMANY  // Not verbose on final too-many-errors error
+            && !m_describedEachWarn[m_errorCode]) {
             m_describedEachWarn[m_errorCode] = true;
-            if (!m_errorCode.hardError() && !m_describedWarnings) {
-                m_describedWarnings = true;
+            const string docUrl = "https://verilator.org/verilator_doc.html"s
+                                  + "?v=" + PACKAGE_VERSION_NUMBER_STRING;
+            const string warnUrl = "https://verilator.org/warn/"s + m_errorCode.ascii()
+                                   + "?v=" + PACKAGE_VERSION_NUMBER_STRING;
+            if (m_errorCode >= V3ErrorCode::EC_FIRST_NAMED) {
+                std::cerr << warnMore() << "... For " << (anError ? "error" : "warning")
+                          << " description see " << warnUrl << endl;
+            } else if (m_errCount >= 1
+                       && (m_errorCode == V3ErrorCode::EC_FATAL
+                           || m_errorCode == V3ErrorCode::EC_FATALMANY
+                           || m_errorCode == V3ErrorCode::EC_FATALSRC)
+                       && !m_tellInternal) {
+                m_tellInternal = true;
+                std::cerr << warnMore()
+                          << "... This fatal error may be caused by the earlier error(s);"
+                             " resolve those first."
+                          << endl;
+            } else if (!m_tellManual) {
+                m_tellManual = true;
+                std::cerr << warnMore() << "... See the manual at " << docUrl
+                          << " for more assistance." << endl;
+            }
+            if (!m_pretendError[m_errorCode] && !m_errorCode.hardError()) {
                 std::cerr << warnMore() << "... Use \"/* verilator lint_off "
                           << m_errorCode.ascii()
                           << " */\" and lint_on around source to disable this message." << endl;
-            }
-            if (m_errorCode.dangerous()) {
-                std::cerr << warnMore() << "*** See https://verilator.org/warn/"
-                          << m_errorCode.ascii() << " before disabling this,\n";
-                std::cerr << warnMore() << "else you may end up with different sim results."
-                          << endl;
+                if (m_errorCode.dangerous()) {
+                    std::cerr << warnMore() << "*** See " << warnUrl
+                              << " before disabling this,\n";
+                    std::cerr << warnMore() << "else you may end up with different sim results."
+                              << endl;
+                }
             }
         }
         if (!msg_additional.empty()) std::cerr << msg_additional;
-        // If first warning is not the user's fault (internal/unsupported) then give the website
-        // Not later warnings, as a internal may be caused by an earlier problem
-        if (tellManual() == 0) {
-            if (m_errorCode.mentionManual() || sstr.str().find("Unsupported") != string::npos) {
-                tellManual(1);
-            } else {
-                tellManual(2);
-            }
-        }
         if (anError) {
             incErrors();
         } else {
             incWarnings();
         }
-        if (m_errorCode == V3ErrorCode::EC_FATAL || m_errorCode == V3ErrorCode::EC_FATALEXIT
+        if (m_errorCode == V3ErrorCode::EC_FATAL || m_errorCode == V3ErrorCode::EC_FATALMANY
             || m_errorCode == V3ErrorCode::EC_FATALSRC) {
             static bool inFatal = false;
             if (!inFatal) {
                 inFatal = true;
-                if (tellManual() == 1) {
-                    std::cerr << warnMore()
-                              << "... See the manual at https://verilator.org/verilator_doc.html "
-                                 "for more assistance."
-                              << endl;
-                    tellManual(2);
-                }
 #ifndef V3ERROR_NO_GLOBAL_
                 if (dumpTreeLevel() || dumpTreeJsonLevel() || debug()) {
                     V3Broken::allowMidvisitorCheck(true);
@@ -271,12 +271,12 @@ string V3Error::lineStr(const char* filename, int lineno) VL_PURE {
 void V3Error::abortIfWarnings() {
     const bool exwarn = warnFatal() && warnCount();
     if (errorCount() && exwarn) {
-        v3fatalExit("Exiting due to " << std::dec << V3Error::s().errorCount() << " error(s), "  //
+        v3fatalMany("Exiting due to " << std::dec << V3Error::s().errorCount() << " error(s), "  //
                                       << V3Error::s().warnCount() << " warning(s)\n");
     } else if (errorCount()) {
-        v3fatalExit("Exiting due to " << std::dec << V3Error::s().errorCount() << " error(s)\n");
+        v3fatalMany("Exiting due to " << std::dec << V3Error::s().errorCount() << " error(s)\n");
     } else if (exwarn) {
-        v3fatalExit("Exiting due to " << std::dec << V3Error::s().warnCount() << " warning(s)\n");
+        v3fatalMany("Exiting due to " << std::dec << V3Error::s().warnCount() << " warning(s)\n");
     }
 }
 

src/V3Error.h

@@ -44,7 +44,7 @@ public:
         //
         EC_INFO,        // General information out
         EC_FATAL,       // Kill the program
-        EC_FATALEXIT,   // Kill the program, suppress with --quiet-exit
+        EC_FATALMANY,   // Kill the program, due to too many errors, suppress with --quiet-exit
         EC_FATALSRC,    // Kill the program, for internal source errors
         EC_ERROR,       // General error out, can't suppress
         EC_FIRST_NAMED,  // Just a code so the program knows where to start info/errors
@@ -186,7 +186,7 @@ public:
         // clang-format off
         static const char* const names[] = {
             // Leading spaces indicate it can't be disabled.
-            " MIN", " INFO", " FATAL", " FATALEXIT", " FATALSRC", " ERROR", " FIRST_NAMED",
+            " MIN", " INFO", " FATAL", " FATALMANY", " FATALSRC", " ERROR", " FIRST_NAMED",
             // Boolean
             " I_CELLDEFINE", " I_COVERAGE",  " I_DEF_NETTYPE_WIRE", " I_LINT", " I_TIMING", " I_TRACING", " I_UNUSED",
             // Errors
@@ -313,9 +313,9 @@ public:
 private:
     static constexpr unsigned MAX_ERRORS = 50;  // Fatal after this may errors
 
-    bool m_describedWarnings VL_GUARDED_BY(m_mutex) = false;  // Told user how to disable warns
     // Tell user to see manual, 0=not yet, 1=doit, 2=disable
-    int m_tellManual VL_GUARDED_BY(m_mutex) = 0;
+    bool m_tellManual VL_GUARDED_BY(m_mutex) = false;
+    bool m_tellInternal VL_GUARDED_BY(m_mutex) = false;
     V3ErrorCode m_errorCode VL_GUARDED_BY(m_mutex)
         = V3ErrorCode::EC_FATAL;  // Error string being formed will abort
     bool m_errorSuppressed VL_GUARDED_BY(m_mutex)
@@ -328,7 +328,6 @@ private:
     int m_errCount VL_GUARDED_BY(m_mutex) = 0;  // Error count
     // Pretend this warning is an error
     std::array<bool, V3ErrorCode::_ENUM_MAX> m_pretendError VL_GUARDED_BY(m_mutex);
-    bool m_describedWeb VL_GUARDED_BY(m_mutex) = false;  // Told user to see web
     // Told user specifics about this warning
     std::array<bool, V3ErrorCode::_ENUM_MAX> m_describedEachWarn VL_GUARDED_BY(m_mutex);
     int m_debugDefault = 0;  // Option: --debugi Default debugging level
@@ -364,7 +363,7 @@ public:
         m_errCount++;
         if (errorCount() == errorLimit()) {  // Not >= as would otherwise recurse
             v3errorEnd(
-                (v3errorPrep(V3ErrorCode::EC_FATALEXIT),
+                (v3errorPrep(V3ErrorCode::EC_FATALMANY),
                  (v3errorStr() << "Exiting due to too many errors encountered; --error-limit="
                                << errorCount() << std::endl),
                  v3errorStr()));
@@ -393,18 +392,12 @@ public:
     int warnCount() VL_REQUIRES(m_mutex) { return m_warnCount; }
     bool errorSuppressed() VL_REQUIRES(m_mutex) { return m_errorSuppressed; }
     void errorSuppressed(bool flag) VL_REQUIRES(m_mutex) { m_errorSuppressed = flag; }
-    bool describedWeb() VL_REQUIRES(m_mutex) { return m_describedWeb; }
-    void describedWeb(bool flag) VL_REQUIRES(m_mutex) { m_describedWeb = flag; }
     bool describedEachWarn(V3ErrorCode code) VL_REQUIRES(m_mutex) {
         return m_describedEachWarn[code];
     }
     void describedEachWarn(V3ErrorCode code, bool flag) VL_REQUIRES(m_mutex) {
         m_describedEachWarn[code] = flag;
     }
-    bool describedWarnings() VL_REQUIRES(m_mutex) { return m_describedWarnings; }
-    void describedWarnings(bool flag) VL_REQUIRES(m_mutex) { m_describedWarnings = flag; }
-    int tellManual() VL_REQUIRES(m_mutex) { return m_tellManual; }
-    void tellManual(int level) VL_REQUIRES(m_mutex) { m_tellManual = level; }
     void suppressThisWarning() VL_REQUIRES(m_mutex);
     string warnContextNone() VL_REQUIRES(m_mutex) {
         errorContexted(true);
@@ -567,7 +560,7 @@ void v3errorEndFatal(std::ostringstream& sstr)
 #define v3error(msg) v3warnCode(V3ErrorCode::EC_ERROR, msg)
 #define v3fatal(msg) v3warnCodeFatal(V3ErrorCode::EC_FATAL, msg)
 // Fatal exit; used instead of fatal() if message gets suppressed with --quiet-exit
-#define v3fatalExit(msg) v3warnCodeFatal(V3ErrorCode::EC_FATALEXIT, msg)
+#define v3fatalMany(msg) v3warnCodeFatal(V3ErrorCode::EC_FATALMANY, msg)
 // Fatal exit; used instead of fatal() to mention the source code line
 #define v3fatalSrc(msg) \
     v3errorEndFatal(v3errorBuildMessage( \

src/V3Options.cpp

@@ -930,7 +930,7 @@ void V3Options::notify() VL_MT_DISABLED {
     }
 
     if (trace()) {
-        // With --trace, --trace-threads is ignored
+        // With --trace-vcd, --trace-threads is ignored
         if (traceFormat().vcd()) m_traceThreads = 1;
     }
 
@@ -1671,6 +1671,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
     });
     DECL_OPTION("-no-trace-top", Set, &m_noTraceTop);
     DECL_OPTION("-trace-underscore", OnOff, &m_traceUnderscore);
+    DECL_OPTION("-trace-vcd", CbCall, [this]() {
+        m_trace = true;
+        m_traceFormat = TraceFormat::VCD;
+    });
 
     DECL_OPTION("-U", CbPartialMatch, &V3PreShell::undef);
     DECL_OPTION("-underline-zero", OnOff, &m_underlineZero);  // Deprecated

test_regress/driver.py

@@ -1036,7 +1036,7 @@ class VlTest:
         if Args.rr:
             verilator_flags += ["--rr"]
         if Args.trace:
-            verilator_flags += ["--trace"]
+            verilator_flags += ["--trace-vcd"]
         if Args.gdbsim or Args.rrsim:
             verilator_flags += ["-CFLAGS -ggdb -LDFLAGS -ggdb"]
         verilator_flags += ["--x-assign unique"]  # More likely to be buggy
@@ -2382,6 +2382,7 @@ class VlTest:
         out = test.run_capture(cmd, check=True)
         if out != '':
             print(out)
+            self.copy_if_golden(fn1, fn2)
             self.error("SAIF files don't match!")
 
     def _vcd_read(self, filename: str) -> str:

test_regress/t/t_a1_first_cc.py

@@ -26,7 +26,7 @@ test.run(
     ],
     verilator_run=True)
 
-test.compile(verilator_flags2=[DEBUG_QUIET, "--trace"])
+test.compile(verilator_flags2=[DEBUG_QUIET, "--trace-vcd"])
 
 test.execute()
 

test_regress/t/t_a2_first_sc.py

@@ -18,7 +18,7 @@ test.top_filename = "t/t_a1_first_cc.v"
 
 DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"
 
-test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace"])
+test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace-vcd"])
 
 test.execute()
 

test_regress/t/t_array_backw_index_bad.out

@@ -2,6 +2,7 @@
                                          : ... note: In instance 't'
    17 |       array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
       |                   ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]'
                                          : ... note: In instance 't'
    18 |       larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};

test_regress/t/t_array_list_bad.out

@@ -2,6 +2,7 @@
                                   : ... note: In instance 't'
    38 |             test_out <= '{'0, '0};  
       |                         ^~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
                                                 : ... note: In instance 't'
    38 |             test_out <= '{'0, '0};  

test_regress/t/t_array_method_bad.out

@@ -2,4 +2,5 @@
                                    : ... note: In instance 't'
    11 |       q.mex;
       |         ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_array_method_map.out

@@ -7,4 +7,5 @@
                                     : ... note: In instance 't'
    17 |       res = a.map(el) with (el == 200);
       |               ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_array_method_unsup.out

@@ -2,6 +2,7 @@
                                       : ... note: In instance 't'
    23 |       i = q.sum with (item + 1); do if ((i) !== (32'h11)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", "t/t_array_method_unsup.v",23, (i), (32'h11)); $stop; end while(0);;
       |                 ^~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_array_method_unsup.v:24:21: 'with' not legal on this method
                                       : ... note: In instance 't'
    24 |       i = q.product with (item + 1); do if ((i) !== (32'h168)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", "t/t_array_method_unsup.v",24, (i), (32'h168)); $stop; end while(0);;

test_regress/t/t_array_pattern_bad.out

@@ -2,4 +2,5 @@
                                      : ... note: In instance 't'
    24 |                  valids: '1};
       |                  ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_array_pattern_bad2.out

@@ -2,4 +2,5 @@
                                       : ... note: In instance 't'
    22 |       myinfo = '{default: '0,
       |                ^~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_array_pattern_bad3.out

@@ -2,6 +2,7 @@
                                       : ... note: In instance 't'
    20 |               1: '1};   
       |               ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_array_pattern_bad3.v:21:13: Assignment pattern with too many elements
                                       : ... note: In instance 't'
    21 |       arr = '{'0, '1, '0, '1};   

test_regress/t/t_assert_comp_bad.out

@@ -24,6 +24,8 @@
                                               : ... note: In instance 't'
    15 |       $error;
       |       ^~~~~~
+                    ... For warning description see https://verilator.org/warn/USERERROR?v=latest
+                    ... Use "/* verilator lint_off USERERROR */" and lint_on around source to disable this message.
 %Warning-USERERROR: t/t_assert_comp_bad.v:16:7: User elaboration-time error
                                               : ... note: In instance 't'
    16 |       $error("User elaboration-time error");
@@ -32,6 +34,8 @@
                                               : ... note: In instance 't'
    17 |       $fatal(0, "User elaboration-time fatal");
       |       ^~~~~~
+                    ... For warning description see https://verilator.org/warn/USERFATAL?v=latest
+                    ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
 %Warning-USERFATAL: t/t_assert_comp_bad.v:18:7: Elaboration system task message (IEEE 1800-2023 20.11)
                                               : ... note: In instance 't'
    18 |       $fatal;

test_regress/t/t_assert_ctl_arg.py

@@ -19,6 +19,6 @@ test.compile(
 
 test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename)
 
-test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg_coverage.out")
+test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg.coverage.out")
 
 test.passes()

test_regress/t/t_assert_ctl_arg_coverage.out

@@ -1,153 +0,0 @@
-# SystemC::Coverage-3
-C '
ft/t_assert_ctl_arg.v
l100
n32
pagev_user/t
ocover_simple_immediate_100
htop.t.cover_simple_immediate_100' 1
-C '
ft/t_assert_ctl_arg.v
l100
n37
pagev_user/t
ocover_simple_immediate_stmt_100
htop.t.cover_simple_immediate_stmt_100' 1
-C '
ft/t_assert_ctl_arg.v
l100
n40
pagev_user/t
ocover_final_deferred_immediate_100
htop.t.cover_final_deferred_immediate_100' 1
-C '
ft/t_assert_ctl_arg.v
l100
n43
pagev_user/t
ocover_observed_deferred_immediate_100
htop.t.cover_observed_deferred_immediate_100' 1
-C '
ft/t_assert_ctl_arg.v
l100
n45
pagev_user/t
ocover_final_deferred_immediate_stmt_100
htop.t.cover_final_deferred_immediate_stmt_100' 1
-C '
ft/t_assert_ctl_arg.v
l100
n48
pagev_user/t
ocover_observed_deferred_immediate_stmt_100
htop.t.cover_observed_deferred_immediate_stmt_100' 1
-C '
ft/t_assert_ctl_arg.v
l103
n32
pagev_user/t
ocover_simple_immediate_103
htop.t.cover_simple_immediate_103' 0
-C '
ft/t_assert_ctl_arg.v
l103
n37
pagev_user/t
ocover_simple_immediate_stmt_103
htop.t.cover_simple_immediate_stmt_103' 0
-C '
ft/t_assert_ctl_arg.v
l103
n40
pagev_user/t
ocover_final_deferred_immediate_103
htop.t.cover_final_deferred_immediate_103' 0
-C '
ft/t_assert_ctl_arg.v
l103
n43
pagev_user/t
ocover_observed_deferred_immediate_103
htop.t.cover_observed_deferred_immediate_103' 0
-C '
ft/t_assert_ctl_arg.v
l103
n45
pagev_user/t
ocover_final_deferred_immediate_stmt_103
htop.t.cover_final_deferred_immediate_stmt_103' 0
-C '
ft/t_assert_ctl_arg.v
l103
n48
pagev_user/t
ocover_observed_deferred_immediate_stmt_103
htop.t.cover_observed_deferred_immediate_stmt_103' 0
-C '
ft/t_assert_ctl_arg.v
l106
n32
pagev_user/t
ocover_simple_immediate_106
htop.t.cover_simple_immediate_106' 1
-C '
ft/t_assert_ctl_arg.v
l106
n37
pagev_user/t
ocover_simple_immediate_stmt_106
htop.t.cover_simple_immediate_stmt_106' 1
-C '
ft/t_assert_ctl_arg.v
l106
n40
pagev_user/t
ocover_final_deferred_immediate_106
htop.t.cover_final_deferred_immediate_106' 1
-C '
ft/t_assert_ctl_arg.v
l106
n43
pagev_user/t
ocover_observed_deferred_immediate_106
htop.t.cover_observed_deferred_immediate_106' 1
-C '
ft/t_assert_ctl_arg.v
l106
n45
pagev_user/t
ocover_final_deferred_immediate_stmt_106
htop.t.cover_final_deferred_immediate_stmt_106' 1
-C '
ft/t_assert_ctl_arg.v
l106
n48
pagev_user/t
ocover_observed_deferred_immediate_stmt_106
htop.t.cover_observed_deferred_immediate_stmt_106' 1
-C '
ft/t_assert_ctl_arg.v
l108
n32
pagev_user/t
ocover_simple_immediate_108
htop.t.cover_simple_immediate_108' 1
-C '
ft/t_assert_ctl_arg.v
l108
n37
pagev_user/t
ocover_simple_immediate_stmt_108
htop.t.cover_simple_immediate_stmt_108' 1
-C '
ft/t_assert_ctl_arg.v
l108
n40
pagev_user/t
ocover_final_deferred_immediate_108
htop.t.cover_final_deferred_immediate_108' 1
-C '
ft/t_assert_ctl_arg.v
l108
n43
pagev_user/t
ocover_observed_deferred_immediate_108
htop.t.cover_observed_deferred_immediate_108' 1
-C '
ft/t_assert_ctl_arg.v
l108
n45
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-C '
ft/t_assert_ctl_arg.v
l92
n42
pagev_user/t
ocover_observed_deferred_immediate_92
htop.t.cover_observed_deferred_immediate_92' 0
-C '
ft/t_assert_ctl_arg.v
l92
n44
pagev_user/t
ocover_final_deferred_immediate_stmt_92
htop.t.cover_final_deferred_immediate_stmt_92' 0
-C '
ft/t_assert_ctl_arg.v
l92
n47
pagev_user/t
ocover_observed_deferred_immediate_stmt_92
htop.t.cover_observed_deferred_immediate_stmt_92' 0
-C '
ft/t_assert_ctl_arg.v
l97
n31
pagev_user/t
ocover_simple_immediate_97
htop.t.cover_simple_immediate_97' 0
-C '
ft/t_assert_ctl_arg.v
l97
n36
pagev_user/t
ocover_simple_immediate_stmt_97
htop.t.cover_simple_immediate_stmt_97' 0
-C '
ft/t_assert_ctl_arg.v
l97
n39
pagev_user/t
ocover_final_deferred_immediate_97
htop.t.cover_final_deferred_immediate_97' 0
-C '
ft/t_assert_ctl_arg.v
l97
n42
pagev_user/t
ocover_observed_deferred_immediate_97
htop.t.cover_observed_deferred_immediate_97' 0
-C '
ft/t_assert_ctl_arg.v
l97
n44
pagev_user/t
ocover_final_deferred_immediate_stmt_97
htop.t.cover_final_deferred_immediate_stmt_97' 0
-C '
ft/t_assert_ctl_arg.v
l97
n47
pagev_user/t
ocover_observed_deferred_immediate_stmt_97
htop.t.cover_observed_deferred_immediate_stmt_97' 0

test_regress/t/t_assert_ctl_arg_noinl.py

@@ -23,6 +23,6 @@ test.compile(make_top_shell=False,
 test.execute(all_run_flags=["+verilator+error+limit+100"],
              expect_filename=test.t_dir + "/t_assert_ctl_arg.out")
 
-test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg_coverage.out")
+test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg.coverage.out")
 
 test.passes()

test_regress/t/t_assert_ctl_unsup.out

@@ -31,6 +31,7 @@
 %Error: t/t_assert_ctl_unsup.v:38:7: Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)
    38 |       $assertcontrol(0);
       |       ^~~~~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_assert_ctl_unsup.v:39:7: Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)
    39 |       $assertcontrol(100);
       |       ^~~~~~~~~~~~~~

test_regress/t/t_assert_disable_bad.out

@@ -2,4 +2,5 @@
                                       : ... note: In instance 't'
    27 |    assert property (disable iff (val == 0) check(1, 1));
       |                                      ^~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_assert_dup_bad.out

@@ -4,4 +4,5 @@
         t/t_assert_dup_bad.v:15:4: ... Location of original declaration
    15 |    covlabel:
       |    ^~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_assert_imm_nz_bad.out

@@ -1,4 +1,5 @@
 %Error: t/t_assert_imm_nz_bad.v:13:26: Deferred assertions must use '#0' (IEEE 1800-2023 16.4)
    13 |    labeled_imas: assert #1 (clk);   
       |                          ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_assert_procedural_clk_bad.out

@@ -2,6 +2,7 @@
                                              : ... note: In instance 't'
    21 |             assume property (@(posedge clk) cyc == 9);
       |             ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_assert_procedural_clk_bad.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
                                              : ... note: In instance 't'
    22 |             assume property (@(negedge clk) cyc == 9);

test_regress/t/t_assert_property_var_unsup.out

@@ -5,10 +5,11 @@
 %Error: t/t_assert_property_var_unsup.v:18:7: syntax error, unexpected '(', expecting endproperty
    18 |       (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1);
       |       ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error-UNSUPPORTED: t/t_assert_property_var_unsup.v:24:31: Unsupported: property variable default value
    24 |    property with_def(int nine = 9);
       |                               ^
 %Error: Internal Error: t/t_assert_property_var_unsup.v:7:8: ../V3ParseSym.h:#: Symbols suggest ending PROPERTY 'prop' but parser thinks ending MODULE 't'
     7 | module t ( 
       |        ^
-                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
+                        ... This fatal error may be caused by the earlier error(s); resolve those first.

test_regress/t/t_assoc_method_bad.out

@@ -2,6 +2,7 @@
                                     : ... note: In instance 't'
    14 |       v = a.num("badarg");
       |             ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_assoc_method_bad.v:15:13: The 1 arguments passed to .size method does not match its requiring 0 arguments
                                     : ... note: In instance 't'
    15 |       v = a.size("badarg");

test_regress/t/t_assoc_nokey_bad.out

@@ -2,6 +2,7 @@
                                    : ... note: In instance 't'
    12 |       int dict[string] = '{1, 2};
       |                            ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_assoc_nokey_bad.v:12:31: Missing pattern key (need an expression then a ':')
                                    : ... note: In instance 't'
    12 |       int dict[string] = '{1, 2};

test_regress/t/t_assoc_wildcard_bad.out

@@ -2,6 +2,7 @@
                                       : ... note: In instance 't'
    23 |       v = a.num("badarg");
       |             ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_assoc_wildcard_bad.v:24:13: The 1 arguments passed to .size method does not match its requiring 0 arguments
                                       : ... note: In instance 't'
    24 |       v = a.size("badarg");

test_regress/t/t_bigmem_bad.out

@@ -2,6 +2,7 @@
                               : ... note: In instance 't_bigmem'
    14 |       if (wen) mem[addr] <= data;
       |                   ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Warning-WIDTHTRUNC: t/t_bigmem_bad.v:14:26: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits.
                                            : ... note: In instance 't_bigmem'
    14 |       if (wen) mem[addr] <= data;

test_regress/t/t_bitsel_const_bad.out

@@ -2,4 +2,5 @@
                                     : ... note: In instance 't'
    16 |    assign a = b[0];   
       |                ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_bitsel_wire_array_bad.out

@@ -2,4 +2,5 @@
                                          : ... note: In instance 't'
    16 |    assign b = a[0];   
       |                ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_case_default_bad.out

@@ -1,4 +1,5 @@
 %Error: t/t_case_default_bad.v:16:9: Multiple default statements in case statement.
    16 |         default: $stop;
       |         ^~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_case_genx_bad.out

@@ -2,4 +2,5 @@
                                 : ... note: In instance 't'
    14 |         32'b1xxx: initial begin end
       |         ^~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_case_incrdecr.py

@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["--trace --fno-split -x-assign 0"])
+test.compile(verilator_flags2=["--trace-vcd --fno-split -x-assign 0"])
 
 test.execute()
 

test_regress/t/t_case_inside_bad.out

@@ -1,4 +1,5 @@
 %Error: t/t_case_inside_bad.v:9:20: Illegal to have inside on a casex/casez
     9 |       casex (1'bx) inside
       |                    ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_case_x_bad.out

@@ -6,4 +6,6 @@
 %Warning-CASEWITHX: t/t_case_x_bad.v:19:9: Use of x/? constant in case statement, (perhaps intended casex/casez)
    19 |         4'b1xxx: $stop;
       |         ^~~~~~~
+                    ... For warning description see https://verilator.org/warn/CASEWITHX?v=latest
+                    ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message.
 %Error: Exiting due to

test_regress/t/t_cast_class_incompat_bad.out

@@ -3,6 +3,7 @@
                                            : ... Suggest dynamic $cast
    26 |       cls_ab = BaseExtended'(cls_a);   
       |                            ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_cast_class_incompat_bad.v:27:20: Incompatible types to static cast to 'class{}Other' from 'class{}BaseExtended'
                                            : ... note: In instance 't'
    27 |       other = Other'(cls_ab);   

test_regress/t/t_cast_size_bad.out

@@ -2,6 +2,7 @@
                                  : ... note: In instance 't'
    14 |       b = (-1)'(a);   
       |               ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Warning-WIDTHEXPAND: t/t_cast_size_bad.v:14:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
                                               : ... note: In instance 't'
    14 |       b = (-1)'(a);   

test_regress/t/t_ccache_report.py

@@ -19,7 +19,7 @@ if not test.cfg_with_ccache:
 for filename in glob.glob(test.obj_dir + "/*.o"):
     test.unlink_ok(filename)
 
-test.compile(verilator_flags2=['--trace'], make_flags=["ccache-report"])
+test.compile(verilator_flags2=['--trace-vcd'], make_flags=["ccache-report"])
 
 report = test.obj_dir + "/" + test.vm_prefix + "__ccache_report.txt"
 

test_regress/t/t_class_assign_bad.out

@@ -2,6 +2,7 @@
                                    : ... note: In instance 't'
    28 |       c = 0;
       |         ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_assign_bad.v:29:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
                                    : ... note: In instance 't'
    29 |       c = 1;

test_regress/t/t_class_assign_cond_bad.out

@@ -2,6 +2,7 @@
                                          : ... note: In instance 't'
    22 |       c1 = (c1 != null) ? c1 : c2;
       |                         ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_assign_cond_bad.v:23:10: Assign RHS expects a CLASSREFDTYPE 'Cls1', got CLASSREFDTYPE 'Cls2'
                                          : ... note: In instance 't'
    23 |       c1 = (c1 != null) ? c2 : c2;

test_regress/t/t_class_builtin_bad.out

@@ -2,6 +2,7 @@
                                     : ... note: In instance 't'
     8 |    function int rand_mode(bit onoff);
       |                 ^~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_builtin_bad.v:11:17: The 'constraint_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.9)
                                      : ... note: In instance 't'
    11 |    function int constraint_mode(bit onoff);

test_regress/t/t_class_copy_bad.out

@@ -2,4 +2,5 @@
                                   : ... note: In instance 't'
    19 |       c1 = new co;   
       |                ^~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_extends_aliased_real_bad.out

@@ -2,4 +2,5 @@
                                                   : ... note: In instance 't'
    14 |    bar #(real_t) bar_real_t;
       |          ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_extends_bad.out

@@ -1,4 +1,5 @@
 %Error: t/t_class_extends_bad.v:13:26: Multiple inheritance illegal on non-interface classes (IEEE 1800-2023 8.13)
    13 | class Cls extends Base1, Base2;
       |                          ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_extends_int_param_bad.out

@@ -2,4 +2,5 @@
                                               : ... note: In instance 't'
     9 |    class Bar #(type T=int) extends T;
       |                       ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_extends_nf_bad.out

@@ -2,6 +2,7 @@
                                         : ... Suggested alternative: 'IsFound'
    15 | class Cls extends IsNotFound;   
       |                   ^~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_extends_nf_bad.v:18:25: Class for 'extends' not found: 'NotFound2'
                                         : ... Suggested alternative: 'otFound2'
    18 | class Cls2 extends Pkg::NotFound2;   

test_regress/t/t_class_extends_rec_bad.out

@@ -1,4 +1,5 @@
 %Error: t/t_class_extends_rec_bad.v:7:31: Attempting to extend class 'RecursiveExtCls' from itself
     7 | class RecursiveExtCls extends RecursiveExtCls;
       |                               ^~~~~~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_extern_bad.out

@@ -4,6 +4,7 @@
         t/t_class_extern_bad.v:8:16: ... Location of original declaration
     8 |    extern task nodef();
       |                ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_extern_bad.v:8:16: Definition not found for extern 'nodef'
     8 |    extern task nodef();
       |                ^~~~~

test_regress/t/t_class_func_nvoid_bad.out

@@ -2,6 +2,7 @@
                                         : ... note: In instance 't'
    47 |       if (mod_fv() == 10) $stop;   
       |           ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_func_nvoid_bad.v:50:11: Cannot call a task/void-function as a function: 'mod_t'
                                         : ... note: In instance 't'
    50 |       if (mod_t() == 10) $stop;   

test_regress/t/t_class_member_bad.out

@@ -3,6 +3,7 @@
                                    : ... Suggested alternative: 'memb2'
    18 |       c.memb3 = 3;   
       |         ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Warning-WIDTHTRUNC: t/t_class_member_bad.v:18:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh3' generates 32 or 2 bits.
                                                  : ... note: In instance 't'
    18 |       c.memb3 = 3;   

test_regress/t/t_class_member_bad2.out

@@ -4,6 +4,7 @@
         t/t_class_member_bad2.v:8:8: ... Location of original declaration
     8 |    int vardup;
       |        ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of task: 'memdup'
    12 |    task memdup;
       |         ^~~~~~

test_regress/t/t_class_member_var_virt_bad.out

@@ -1,4 +1,5 @@
 %Error: t/t_class_member_var_virt_bad.v:8:16: Syntax error: 'virtual' not allowed before var declaration
     8 |    virtual int member;
       |                ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_method_bad.out

@@ -3,4 +3,5 @@
                                    : ... Suggested alternative: 'meth2'
    18 |       c.meth3();   
       |         ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_mispure_bad.out

@@ -4,4 +4,5 @@
         t/t_class_mispure_bad.v:8:31: ... Location of interface class's function
     8 |    pure virtual function void pvfunc();
       |                               ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_misstatic_bad.out

@@ -2,6 +2,7 @@
                                       : ... note: In instance 't'
    31 |       nonstatic();   
       |       ^~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_misstatic_bad.v:38:12: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10)
                                        : ... note: In instance 't'
    38 |       Cls::nonstatic();   

test_regress/t/t_class_mod_bad.out

@@ -1,6 +1,7 @@
 %Error: t/t_class_mod_bad.v:21:7: Package/class for ':: reference' not found: 'M'
    21 |       M::Cls p;
       |       ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_mod_bad.v:21:7: Package/class for 'class/package reference' not found: 'M'
    21 |       M::Cls p;
       |       ^

test_regress/t/t_class_new_bad.out

@@ -2,6 +2,7 @@
                                  : ... note: In instance 't'
    31 |       c1 = new(3);   
       |                ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_new_bad.v:32:16: Too many arguments in function call to FUNC 'new'
                                  : ... note: In instance 't'
    32 |       c2 = new(3);   
@@ -18,3 +19,4 @@
                                                  : ... note: In instance 't'
    34 |       c1 = new[2];
       |            ^~~
+                        ... This fatal error may be caused by the earlier error(s); resolve those first.

test_regress/t/t_class_new_ref_bad.out

@@ -2,6 +2,7 @@
                                      : ... note: In instance 't'
    16 |       txn_type_t txn = new;
       |                        ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_new_ref_bad.v:17:25: new() cannot copy from non-class data type 'int'
                                      : ... note: In instance 't'
    17 |       txn_type_t copy = new txn;

test_regress/t/t_class_new_scoped.out

@@ -1,6 +1,7 @@
 %Error: t/t_class_new_scoped.v:45:21: syntax error, unexpected new, expecting IDENTIFIER-for-type
    45 |       b = ClsNoArg::new;
       |                     ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_new_scoped.v:50:19: syntax error, unexpected new-then-paren, expecting IDENTIFIER-for-type
    50 |       b = ClsArg::new(20, 1);
       |                   ^~~

test_regress/t/t_class_override_bad.out

@@ -2,6 +2,7 @@
                                       : ... note: In instance 't'
    22 |    function :extends int get_e; return 1; endfunction   
       |                          ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_override_bad.v:24:33: Member 'get_ef' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20)
                                       : ... note: In instance 't'
    24 |    function :extends :final int get_ef; return 1; endfunction   

test_regress/t/t_class_param_bad2.out

@@ -2,6 +2,7 @@
                                    : ... note: In instance 't'
    12 |    Cls c;   
       |    ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_param_bad2.v:7:18: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'PARAMB'
                                    : ... note: In instance 't'
     7 | class Cls #(type PARAMB);

test_regress/t/t_class_param_bad_paren.out

@@ -2,4 +2,5 @@
                                          : ... Suggest use 'Cls#()'
    28 |       if (Cls::OTHER != 12) $stop;   
       |           ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_param_circ_bad.out

@@ -2,4 +2,6 @@
                                        : ... note: In instance 't'
    14 |    ClsA #(PARAM+1) a;
       |    ^~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Internal Error: ../V3Param.cpp:#: should find just-made module
+                        ... This fatal error may be caused by the earlier error(s); resolve those first.

test_regress/t/t_class_param_comma_bad.out

@@ -1,6 +1,7 @@
 %Error: t/t_class_param_comma_bad.v:16:22: syntax error, unexpected ')', expecting IDENTIFIER-for-type
    16 |    Cls #(.PARAMB(14),) ce;   
       |                      ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_param_comma_bad.v:17:13: syntax error, unexpected ')', expecting IDENTIFIER-for-type
    17 |    Cls #(14,) cf;   
       |             ^

test_regress/t/t_class_param_enum_bad.out

@@ -2,6 +2,7 @@
                                         : ... note: In instance 't'
    20 |       Converter#(bit) conv2 = conv1;
       |                               ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error-ENUMVALUE: t/t_class_param_enum_bad.v:21:19: Implicit conversion to enum 'enum{}$unit::enum_t' from 'logic[31:0]' (IEEE 1800-2023 6.19.3)
                                                   : ... note: In instance 't'
                                                   : ... Suggest use enum's mnemonic, or static cast

test_regress/t/t_class_param_nconst_bad.out

@@ -2,6 +2,7 @@
                                           : ... note: In instance 't'
    12 |    Cls #(.PARAM($random)) c;   
       |                 ^~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_param_nconst_bad.v:12:11: Can't convert defparam value to constant: Param 'PARAM' of 'Cls'
                                           : ... note: In instance 't'
    12 |    Cls #(.PARAM($random)) c;   

test_regress/t/t_class_param_nested_bad.out

@@ -8,3 +8,4 @@
                                                           : ... note: In instance 't'
    51 |    Wrap2 #(Wrap#(19)::PBASE * 2) w38;
       |                             ^
+                        ... This fatal error may be caused by the earlier error(s); resolve those first.

test_regress/t/t_class_param_noinit_bad.out

@@ -2,6 +2,7 @@
                                          : ... note: In instance 't'
    13 |       Cls #(1) c;   
       |       ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_param_noinit_bad.v:13:7: Class parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T'
                                          : ... note: In instance 't'
    13 |       Cls #(1) c;   

test_regress/t/t_class_param_subtype_bad_paren.out

@@ -2,4 +2,5 @@
                                       : ... Suggest use 'CParam#()'
    32 |     CParam::type_t val_0 = 100;
       |     ^~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_param_virtual_bad.out

@@ -2,6 +2,7 @@
                                            : ... note: In instance 't'
    13 |       t = new;
       |           ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_param_virtual_bad.v:23:28: Illegal to call 'new' using an abstract virtual class 'ClsVirt' (IEEE 1800-2023 8.21)
                                            : ... note: In instance 't'
    23 |       ClsVirt#(VBase) cv = new;   

test_regress/t/t_class_ref_bad.out

@@ -2,4 +2,5 @@
                                  : ... Suggested alternative: 'ClsRight'
    15 |       s = ClsRigh::m_s;   
       |           ^~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_scope_import.out

@@ -1,4 +1,5 @@
 %Error: t/t_class_scope_import.v:11:14: Import statement directly within a class scope is illegal
    11 |    import pkg::*;
       |              ^~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_super_bad.out

@@ -1,4 +1,5 @@
 %Error: t/t_class_super_bad.v:12:12: 'super' used outside class (IEEE 1800-2023 8.15)
    12 |       super.addr = 2;
       |            ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_super_bad2.out

@@ -1,4 +1,5 @@
 %Error: t/t_class_super_bad2.v:10:12: 'super' used on non-extended class (IEEE 1800-2023 8.15)
    10 |       super.i = 1;   
       |            ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_super_new_bad_nfirst.out

@@ -4,4 +4,5 @@
         t/t_class_super_new_bad_nfirst.v:17:16: ... Location of earlier statement
    17 |       imemberc = 10;
       |                ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_unsup_bad.out

@@ -1,6 +1,7 @@
 %Error: t/t_class_unsup_bad.v:24:21: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration
    24 |    rand typedef int irand_t;
       |                     ^~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_class_unsup_bad.v:25:22: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration
    25 |    randc typedef int icrand_t;
       |                      ^~~~~~~~

test_regress/t/t_class_uses_this_bad.out

@@ -1,4 +1,5 @@
 %Error: t/t_class_uses_this_bad.v:11:12: 'this' used outside class (IEEE 1800-2023 8.11)
    11 |        this.addr = 2;
       |            ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_virtual_bad.out

@@ -2,4 +2,5 @@
                                      : ... note: In instance 't'
    12 |       VBase b = new;   
       |                 ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to