Add support for SystemVerilog soft constraints (IEEE 1800-2017 18.5.13).
Soft constraints are optional - they are satisfied when possible, but
dropped when they conflict with hard constraints.
Implementation:
- Add RANDOMIZER_SOFT to VCMethod enum
- Modify V3Randomize.cpp to use RANDOMIZER_SOFT for soft constraints
- Add soft() method and m_softConstraints vector to VlRandomizer
- Modify next() to try solving with hard+soft constraints first,
then retry with only hard constraints if UNSAT
Test: t_randomize_soft.v tests basic soft constraints, soft constraints
that conflict with hard constraints, and multiple soft constraints.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
This change gets rid of most of the shared pointers and useless memory
allocations. Also takes advantage of higher-arity bvxor/concat to
reduce amount of data sent to the solver.
Signed-off-by: Arkadiusz Kozdra <akozdra@antmicro.com>
Thomas Dybdahl Ahle
Yilou Wang
Wilson Snyder
Yilou Wang
Arkadiusz Kozdra
Krzysztof Bieganski