3 Commits

Author	SHA1	Message	Date
Wilson Snyder	e238a2ca5e	Verilog format	2026-02-22 13:50:01 -05:00
Kamil Rakoczy	3ab89d5be7	Add used language to `--preproc-resolve` output (#5795)	2025-02-25 07:03:25 -05:00
Kamil Rakoczy	2e1fa8f338	Add `--preproc-resolve` for modules in preprocessor output (#5789) ... Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>	2025-02-22 04:47:54 +10:00