verilator

Commit Graph

Author	SHA1	Message	Date
Wilson Snyder	078bb21a89	Add wire data type checking per IEEE.	2025-07-20 07:21:30 -04:00
Geza Lore	59cb53cfbc	Set trigger vector in whole words (#5857 ) Having many triggers still hits a bottleneck in LLVM leading to long compile times. Instead of setting triggers bit-wise, set them as a whole 64-bit word when possible. This improves C++ compile times by ~4x on some large designs and has minor run-time performance benefit.	2025-03-14 14:06:51 +00:00

Author

SHA1

Message

Date

Wilson Snyder

078bb21a89

Add wire data type checking per IEEE.

2025-07-20 07:21:30 -04:00

Geza Lore

59cb53cfbc

Set trigger vector in whole words (#5857 )

Having many triggers still hits a bottleneck in LLVM leading to long
compile times.

Instead of setting triggers bit-wise, set them as a whole 64-bit word
when possible. This improves C++ compile times by ~4x on some large
designs and has minor run-time performance benefit.

2025-03-14 14:06:51 +00:00

2 Commits