verilator

Commit Graph

Author	SHA1	Message	Date
Geza Lore	40ca0527db	Internal: Refactor AstAssignAlias (#6280 ) (#6473 ) Rename AstAssignAlias to AstAlias and make it derive from AstNode instead of AstNodeStmt. Replace AstAlias with AstAssignW in V3LinkDot::linkDotScope, which is the last place we need to be aware of the alias construct. Using AstAssignW dowstream enables further optimization while preserving the same functionality.	2025-09-22 16:30:26 -04:00
Geza Lore	ce77bac99a	Break some combinational cycles in DFG (#6168 ) Added an algorithm that can break some combinational cycles in DFG, by attempting to trace driver logic until we escape the cycle. This can eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code: ```systemverilog assign a[0] = .....; assign a[1] = ~a[0]; ```	2025-07-10 18:46:45 +01:00

Author

SHA1

Message

Date

Geza Lore

40ca0527db

Internal: Refactor AstAssignAlias (#6280 ) (#6473 )

Rename AstAssignAlias to AstAlias and make it derive from AstNode
instead of AstNodeStmt.

Replace AstAlias with AstAssignW in V3LinkDot::linkDotScope, which is
the last place we need to be aware of the alias construct. Using
AstAssignW dowstream enables further optimization while preserving the
same functionality.

2025-09-22 16:30:26 -04:00

Geza Lore

ce77bac99a

Break some combinational cycles in DFG (#6168 )

Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:

```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```

2025-07-10 18:46:45 +01:00

2 Commits