verilator

Commit Graph

Author	SHA1	Message	Date
Geza Lore	77180c4020	Optimize more cycles in DFG (#6173 ) Added a second algorithm to break cycles in DFG by identifying which bits of a circular variable are actually independent of the variable, then reuse the existing (but extended) driver tracing algorithm to eliminate them. This can fix up things like: `assign gray = binary ^ (gray >> 1)`	2025-07-11 14:19:09 -04:00
Geza Lore	ce77bac99a	Break some combinational cycles in DFG (#6168 ) Added an algorithm that can break some combinational cycles in DFG, by attempting to trace driver logic until we escape the cycle. This can eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code: ```systemverilog assign a[0] = .....; assign a[1] = ~a[0]; ```	2025-07-10 18:46:45 +01:00

Author

SHA1

Message

Date

Geza Lore

77180c4020

Optimize more cycles in DFG (#6173 )

Added a second algorithm to break cycles in DFG by identifying which
bits of a circular variable are actually independent of the variable,
then reuse the existing (but extended) driver tracing algorithm to
eliminate them.

This can fix up things like: `assign gray = binary ^ (gray >> 1)`

2025-07-11 14:19:09 -04:00

Geza Lore

ce77bac99a

Break some combinational cycles in DFG (#6168 )

Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:

```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```

2025-07-10 18:46:45 +01:00

2 Commits