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mirror of https://github.com/verilator/verilator.git synced 2026-10-06 01:54:01 +02:00
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6,424 Commits 3 Branches 171 Tags
57c816f906cfcb2657ed2bcbdf815f46556825ca
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6 Commits
Author SHA1 Message Date
Aleksander Kiryk db7935faf3 Add std::process class (#4212) 2023-06-01 10:02:08 -04:00
Wilson Snyder 13a87e5514 Parse process class, and report runtime errors (#3612) 2023-04-08 15:04:42 -04:00
Wilson Snyder 6c21b21ecc Internals: Indent verilated_std.sv with Verilog-mode. No functional change. 2023-04-06 21:27:16 -04:00
Aleksander Kiryk 31130c4b4a Fix std:: to be parsed first (#3864) (#3928) 2023-02-03 09:04:16 -05:00
Wilson Snyder b24d7c83d3 Copyright year update 2023-01-01 10:18:39 -05:00
Wilson Snyder 84c7368621 Rename std.sv and add to install. 2022-12-03 11:31:26 -05:00
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