luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
6,484 Commits 2 Branches 166 Tags 178 MiB
Commit Graph

6484 Commits

Author SHA1 Message Date
Geza Lore 1a056f6db9 Fix invalid conditional merging when starting at 'c = c ? a : b' 
Fixes #3409.
 2022-05-17 18:36:40 +01:00
Krzysztof Bieganski e018eb7bac
Support AstClass::repairCache() after V3Class (#3431) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:22:43 -04:00
Krzysztof Bieganski 0a91ddf38a
Tests: Better grep check in t_foreach (#3435) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:20:59 -04:00
Krzysztof Bieganski 67bb2c640e
Tests: Rename t_timing_clkgen to t_timing_clkgen1 (#3430) 
This is a pre-PR to #3363, which will introduce more clock gen tests.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:19:51 -04:00
Krzysztof Bieganski 561eaa311d
Tests: Enable CI testing with GCC 10 (#3432) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:19:06 -04:00
Geza Lore 282887d9c6 Fix code coverage holes 
Fixes #3422
 2022-05-16 21:22:21 +01:00
Krzysztof Bieganski 3f7a248ed4
Refactor some of the Begin handling to a separate function (#3426) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-16 20:45:33 +01:00
Krzysztof Bieganski ecaa07a72a
Rename AstTimingControl to AstEventControl (#3425) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-16 20:44:41 +01:00
Geza Lore 0e62cd11da Don't issue DEPRECATED for now no-op clock_enable attribute 
Fixes #3421
 2022-05-16 18:57:51 +01:00
Wilson Snyder 99bdc27be3 Internals: Cleanup some statics, trivial part towards (#3419) 2022-05-15 14:26:55 -04:00
Wilson Snyder c3c46967dc Tests: Appease sanitizer (#3121). 2022-05-15 11:50:52 -04:00
Wilson Snyder 7f1a9239ab Commentary, fix typo (#3121) 2022-05-15 11:14:07 -04:00
Geza Lore 599d23697d
IEEE compliant scheduler (#3384) 
This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278
 2022-05-15 16:03:32 +01:00
Geza Lore c8102c8ffe Fix typo 2022-05-15 16:01:35 +01:00
Wilson Snyder 5aa12e9b51 Add assert when VerilatedContext is mis-deleted (#3121). 2022-05-15 10:51:03 -04:00
Geza Lore 829437b20b Commentary - dependencies 2022-05-15 15:25:46 +01:00
Wilson Snyder 3c4131d45d Fix 'with' operator with type casting (#3387). 2022-05-15 09:53:48 -04:00
Wilson Snyder ae8d8ee1ac Fix crash with misuse of display. 2022-05-15 09:29:45 -04:00
Geza Lore 39b7c47e7b Merge branch 'master' into develop-v5 2022-05-15 13:39:14 +01:00
Geza Lore 89ec3d16dc Allow const nodes in VNRef 
No functional change.
 2022-05-15 13:30:07 +01:00
Geza Lore f6f03bc261 Merge branch 'master' into develop-v5 2022-05-15 12:05:12 +01:00
Wilson Snyder 7602c983c5 Commentary 2022-05-14 18:16:31 -04:00
HungMingWu 560efb2c9e
Internals: Fix memory leak in V3FileLine (#3407) (#3408). No functional change intended. 2022-05-14 18:15:38 -04:00
Wilson Snyder c2328ef46a Spelling fixes. 2022-05-14 16:12:57 -04:00
Geza Lore 766fb56651 Merge branch 'master' into develop-v5 2022-05-14 10:30:45 +01:00
Wilson Snyder f6035447ae Internals: Use mutable for mutexes. No functional change. 2022-05-13 07:21:39 -04:00
Wilson Snyder 38438b3373 Internals: Cleanup some defaults. No functional change. 2022-05-12 23:30:39 -04:00
Wilson Snyder 71dedccbbe Support compile time trace signal selection with tracing_on/off (#3323). 2022-05-12 22:28:08 -04:00
Martin Stadler cddbe4642f
Fix cmake rules to support higher-level targest (#3377) (#3386). 
Don't add linker flags as generator expression to support linking `TARGET` to higher-level targets in a top-level CMakeLists.txt file.
 2022-05-11 21:33:05 -04:00
Wilson Snyder bdfdc737a0 Internals: Cleanup V3Config. No functional change intended. 2022-05-11 00:47:52 -04:00
Wilson Snyder 3d045c3aee Internals: Cleanup some verilog.y formatting. No functional change. 2022-05-09 00:37:51 -04:00
HungMingWu 9583f152ee
Fix compile error when enable VL_LEAK_CHECKS (#3411). 
Signed-off-by: HungMingWu <u9089000@gmail.com>
 2022-05-08 20:49:13 -04:00
Wilson Snyder 5b2755d28d Untabify verilog.y (#3412). No functional change. 2022-05-08 20:46:18 -04:00
Geza Lore bec4610e12 Merge branch 'master' into develop-v5 2022-05-08 15:50:50 +01:00
Kamil Rakoczy 9378259779
Fix UNOPTFLAT warning from initial static var (#3406) 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2022-05-06 10:24:03 +02:00
Wilson Snyder 3d762282b9 Fix hang with large case statement optimization (#3405). 2022-05-05 07:02:52 -04:00
Wilson Snyder 184ebe72a2 Merge branch 'master' into develop-v5 2022-05-02 22:27:58 -04:00
Wilson Snyder 30783e6a79 devel release 2022-05-02 22:23:05 -04:00
Wilson Snyder aa86c777f4 Version bump 2022-05-02 22:17:20 -04:00
Geza Lore a2792785fe Add V3GraphVertex::dotRank to add GraphViz ranks to graph dumps 
This is a simple debugging aid to allow constraining the graph layout
via GraphViz rank directives. Note this is not related in any way to the
vertex 'rank' attribute used by some of the graph algorithms.

No functional change.
 2022-05-02 10:27:26 +01:00
Wilson Snyder 267315e7d4 Commentary: Update ChangeLog 2022-05-01 22:01:30 -04:00
Geza Lore 2ad0bcbba9 Merge branch 'master' into develop-v5 2022-05-01 16:49:42 +01:00
Wilson Snyder 99d39cb6ff Fix autoconf warning 2022-05-01 10:43:04 -04:00
Wilson Snyder 915ceb2d04 Tests: Untabify tests. No functional change. 2022-05-01 10:10:00 -04:00
Geza Lore 88bb7cdca6 Merge branch 'master' into develop-v5 2022-04-29 17:14:11 +01:00
Geza Lore 49c90ecbce Issue consistent INITIALDLY/COMBDLY/BLKSEQ warnings 
Some cases of warnings about the use of blocking and non-blocking
assignments in combinational vs sequential processes were suppressed in
a way that is inconsistent with the *actual* current execution model of
Verilator. Turning these back on to, well, warn the user that these might
cause unexpected results. V5 will clean these up, but until then err on
the side of caution.

Fixes #864.
 2022-04-29 17:05:44 +01:00
Geza Lore 8395004d25 Add AstNode::exists and AstNode::forall predicates 2022-04-29 15:44:22 +01:00
Kamil Rakoczy 5de1c619c8
Fix foreach segmentation fault (#3400). 2022-04-28 06:11:31 -04:00
Yoda Lee a6d678d41d
Fix hang in generate symbol references (#3391) (#3398) 2022-04-27 18:40:36 -04:00
Aliaksei Chapyzhenka 2b91d764b5
Added missing #include <memory> (#3392) 
Fixes #3390
 2022-04-23 20:11:46 +01:00