verilator

Commit Graph

Author	SHA1	Message	Date
Wilson Snyder	3a5cbd5b67	Internals: Untabify some embedded tabs.	2021-11-13 10:46:25 -05:00
Yutetsu TAKATSUKASA	f3b10df454	Skip merging assign statements if a variable is marked split_var to fix #3177 (#3179 ) * add tests to reproduce #3177. Any random test circuits can be added to t_split_var_4.v later because it uses CRC to check the result while t_split_var_0.v has just barrel shifters. * Fix #3177. Don't merge assign statements if a variable is marked split_var.	2021-10-25 20:56:59 +09:00

Author

SHA1

Message

Date

Wilson Snyder

3a5cbd5b67

Internals: Untabify some embedded tabs.

2021-11-13 10:46:25 -05:00

Yutetsu TAKATSUKASA

f3b10df454

Skip merging assign statements if a variable is marked split_var to fix #3177 (#3179 )

* add tests to reproduce #3177.

Any random test circuits can be added to t_split_var_4.v later because it uses CRC to check the result while
t_split_var_0.v has just barrel shifters.

* Fix #3177. Don't merge assign statements if a variable is marked split_var.

2021-10-25 20:56:59 +09:00

2 Commits