Commit Graph

23 Commits

Author SHA1 Message Date
Wilson Snyder e1f1c82d4e Fix -E duplicating output, bug1226. 2017-10-09 21:08:50 -04:00
Wilson Snyder e6d7e7e329 Version bump 2017-01-15 12:13:13 -05:00
Wilson Snyder b738d1960a Copyright year update 2016-01-06 20:36:41 -05:00
Wilson Snyder 4fc9a906f6 Internals: Fix cppcheck warnings; add VL_DANGLING. No functional change. 2015-10-04 13:16:35 -04:00
Wilson Snyder 751384cb5c Fix compile error on MinGW, bug887. 2015-02-26 20:40:45 -05:00
Wilson Snyder 4c91ade61d Copyright year update 2015-01-07 18:25:53 -05:00
Wilson Snyder 6da13c6486 Internals: Split V3Error into V3FileLine. No functional change. 2014-11-22 11:48:39 -05:00
Wilson Snyder 0eb5a0a539 Add -P to suppress `line and blanks with preprocessing, bug781. 2014-06-06 20:22:20 -04:00
Wilson Snyder 4422de0c6c Copyright year update. 2014-01-06 19:28:57 -05:00
Wilson Snyder a8bbf7231b Copyright year update. 2013-01-01 09:42:59 -05:00
Wilson Snyder 7a8c425103 Add +1364-1995ext and similar language options, bug532. 2012-11-13 20:12:23 -05:00
Wilson Snyder f0e1d204fa Fix triangle symbol resolution error broke in 3.840, bug550.
This requires the parse symbol table persist across all parse runs. This is
probably more correct than before, but may result in some fallout if people
relied on data types not being persistant across separately parsed cells.
2012-08-15 21:28:30 -04:00
Wilson Snyder c6e7d87960 Commentary - Remove author lines as amany contributors now 2012-05-24 19:19:48 -04:00
Wilson Snyder 50edef4ab2 Add Emacs indentation line. No functional change 2012-04-12 21:08:20 -04:00
Wilson Snyder f13ffe2098 Internals: Merge from VHDL branch. Minor stuff, no functional change. 2012-02-11 20:40:58 -05:00
Wilson Snyder c2c7c7bd9a Copyright year update 2012-01-15 10:26:28 -05:00
Wilson Snyder fb9ca54c95 Fix reporting not found modules if generate-off, bug403. 2011-10-27 20:56:38 -04:00
Wilson Snyder 71c1f00ec2 Copyright year update 2011-01-01 18:21:19 -05:00
Wilson Snyder f8eabbc100 From Verilog-Perl: Fix parsing single files > 2GB. 2010-04-06 20:20:44 -04:00
Wilson Snyder 6196cf09ff Add experimental --pipe-filter to filter all Verilog input. 2010-01-20 07:15:51 -05:00
Wilson Snyder 729dfdfed7 Copyright year update 2010-01-05 21:15:06 -05:00
Wilson Snyder 18bebaf5c3 Internals: Add parse-time symbol table for eventual typedef detection 2009-10-31 10:26:53 -04:00
Wilson Snyder f7efae93d5 Internals: Clean up the main flex/bison files to have some sanity.
(Hopefully) no functional change.
	. V3Parse.h		External consumer interface to V3ParseImp
	. V3ParseImp		Internals to parser, common to across flex & bison
	... V3ParseGrammar	Wrapper that includes V3ParseBison
	..... V3ParseBison	Bison output
	... V3ParseLex		Wrapper that includes lex output
	..... V3Lexer.yy.cpp	Flex output
2009-10-31 10:08:38 -04:00