Commit Graph

65 Commits

Author SHA1 Message Date
Marco Bartoli 645b8cdf24
Support embedded covergroup clocking events (#8028) 2026-08-09 13:55:04 -04:00
Artur Bieniek 1a4bcac666
Support `weak`/`strong` keywords in property expressions (#8054)
Signed-off-by: Artur Bieniek <abieniek@antmicro.com>
2026-08-06 07:48:00 +01:00
BRDR LIFE 5fd1c93d43
Fix randomize() with shadowing a user variable named 'item' (#7993) (#7994)
Fixes #7993.
2026-07-28 12:29:45 -04:00
Philip Axer 8113f1df7a
Fix randomization of unreferenced rand members of unpacked structs (#7910) (#7911)
Fixes #7910.
2026-07-21 07:42:04 -04:00
Yilou Wang 8ed0acf1ec
Support a sequence used as an event control (#7797) (#7846) 2026-07-06 13:12:01 -04:00
Yilou Wang 3a4377d39e
Support clocking event on a sequence declaration body (#7598) (#7793)
Fixes #7598.
2026-06-17 17:57:18 -04:00
Yilou Wang 077558a9b0
Support cover sequence statement (#7764) 2026-06-15 08:36:21 -04:00
Matthew Ballance 2886291eba
Support covergroups, coverpoints, and bins (#784) (#7117)
Fixes #784.
2026-06-05 09:35:01 -04:00
Krzysztof Bieganski eb258d7df7
IEEE-compliant, fair `std::semaphore` (#7435) (#7605)
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2026-05-18 11:11:42 +02:00
Yilou Wang f9427c6d5f
Support property abort operators (accept_on, reject_on) (#7578) 2026-05-15 08:38:38 -04:00
Yilou Wang bc1acc8aa3
Support followed-by operators `#-#` and `#=#` in properties (#7523) 2026-05-04 08:10:37 -04:00
Igor Zaworski 25d4827bd5
Internals: Four state pre-pull (types) (#7520) 2026-04-30 16:56:15 -04:00
Yilou Wang 327fc4ffbe
Support randomize() with (identifier_list) {constraint_block} (#7486) (#7507)
Fixes #7486.
2026-04-28 06:10:53 -04:00
Yilou Wang c8893b64de
Support `always` / `always[m:n]` / `s_always[m:n]` property operators (#7482) 2026-04-27 08:20:34 -04:00
Wilson Snyder 602ee384de
Support $sformat with runtime format string (#7212). (#7257)
Fixes #7212.
2026-03-14 22:43:56 -04:00
Wilson Snyder 7607f0e7fa
Support proper automatic/static initialization, and remove STATICVAR warning (#6405). (#7086) 2026-02-24 14:04:43 -05:00
Geza Lore 1e5a6901c8
Internals: Make AstWith explicit in AstCMethodHard (#7129)
This makes it consistent with other usage in NodeFTaskRef. Also AstWith
is no longer a NodeExpr.
2026-02-22 15:38:28 -05:00
Geza Lore e023113b79
Internals: Carry 'with' clause as op4 on AstNodeFTaskRef (#7114)
op4 is now available to carry the 'with' clause explicitly instead of
being part of the argument lit. Will strengthen 'pinsp' to be
List[AstArg] next.
2026-02-22 09:15:28 +00:00
Wilson Snyder 8700617fae Internals: Cleanup CRESET verilog and other misc fixes 2026-02-08 17:53:56 -05:00
Wilson Snyder 7ca113a84f Fix non-inlined function return value clearing (#6982). 2026-02-01 11:57:09 -05:00
Geza Lore 7875552354
Internals: Add stats/dump of circular logic in scheduling (#6953) 2026-01-28 10:45:23 +00:00
Bartłomiej Chmiel 5adecb9fa3
Support multi-expression sequences (#6639) 2025-11-06 08:42:27 -05:00
Wilson Snyder 01157d414b Optimize constant string arguments before Emit, and cleanup V3EmitV 2025-10-12 20:09:03 -04:00
Bartłomiej Chmiel 31e73f1645
Support simple cycle delay sequence expressions inside assertion properties (#6508)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
2025-10-10 16:16:15 +02:00
Geza Lore f39d6e6108
Deprecate sensitivity list on public_flat_rw attributes (#6443)
These are no longer required for correct scheduling. They are still
accepted for backward compatibility, but have no effect on simulation
and are dropped in the front-end. Also removed the then redundant
AstAlwaysPublic class.

Fixes #6442
2025-09-16 22:38:53 +01:00
Geza Lore d28436dccc
Fix stray ']' in Verilog code output for non-constant select (#6277) 2025-08-09 14:59:58 +01:00
Geza Lore 7c5d462564
Remove AstJumpLabel (#6221)
Remove AstJumpLabel

AstJumpGo now references one if its enclosing AstJumpBlocks, and
branches straight after the referenced block.

That is:

```
JumpBlock a {
   ...
   JumpGo(a);
   ...
}
// <--- the JumpGo(a) goes here
```

This is sufficient for all use cases and makes control flow much easier to
reason about. As a result, V3Const can optimize a bit more aggressively.

Second half of, and fixes #6216
2025-07-23 17:51:16 +01:00
Artur Bieniek abd509ce53
Support delays in emitted Verilog (#6177) 2025-07-16 11:52:56 -04:00
Wilson Snyder f77af4e6f6 Important: Change `--assert` to be the default; use `--no-assert` for legacy behavior and faster runtimes. 2025-07-03 19:36:28 -04:00
Geza Lore 916d473eff
Internals: Replace unnecessary AstSel::widthp() child node with const in node (#6117) 2025-06-24 11:59:09 -04:00
Todd Strader 7336b9ebfc
Add V3EmitV support for sampled value functions (#5931) 2025-04-11 12:25:56 -04:00
Wilson Snyder 53151d7c5f Fix emitting `this` (#5849) 2025-03-11 17:53:35 -04:00
Todd Strader f7ccc013e7
Improve V3EmitV for interfaces (#5796) 2025-02-21 16:49:14 -05:00
Todd Strader 70459b3208
Fix V3EmitV for non-zero based arrays (#5790) 2025-02-21 05:49:32 +11:00
Todd Strader b645fcf027
More V3EmitV support (#5779) 2025-02-14 14:58:11 -05:00
Wilson Snyder 929e15fa4c Fix various round-trip Verilog output, including packed arrays 2025-01-24 21:00:45 -05:00
Bartłomiej Chmiel 35fa0d051d
Support integer atom type ports in `--hierarchical` (#5748) 2025-01-24 07:47:11 -05:00
Wilson Snyder b531001f55 Fix segfault when only enum value referenced in package (#5714). 2025-01-04 10:36:34 -05:00
Wilson Snyder 371a4055b0 Fix false LIFETIME warning on `repeat` in `fork-join` (#5456). 2024-09-18 21:20:17 -04:00
Wilson Snyder de44ca8df3 Fix top-level unpacked structure resets (#5221). 2024-07-05 17:22:26 -04:00
Bartłomiej Chmiel 4695967185
Fix signed types emitted in hierarchical Verilation (#5178)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
2024-06-14 08:07:32 -04:00
Valentin Atepalikhin 4babba16d6
Support 2D dynamic array initialization (#4700) (#5122)
* Support 2D dynamic array initialization (#4700)
- new[] on sub arrays (as per original issue)
- Built-in methods for sub-arrays
- Initialization and literals assignmensts
- Dynamic array as an element for other arrays and queues
2024-06-08 22:44:45 -04:00
Wilson Snyder 2a30bbe493 Fix internal error on real conversion (#4447). 2023-08-29 18:07:23 -04:00
Wilson Snyder 85fd88ace2 Optimize duplicate JumpBlocks away (#4028) 2023-03-16 22:29:06 -04:00
Wilson Snyder 259201b352 Support $fopen as an expression 2023-03-11 18:11:01 -05:00
Wilson Snyder 8a85cedaf5 Tests: Update test, part of (#3378) (#3892) 2023-01-23 07:23:42 -05:00
Aleksander Kiryk c2b09e35f8
Support unpacked structs (#3802) 2022-12-20 19:22:42 -05:00
Wilson Snyder 86b07423a9 Fix ENUMVALUE on parameter (#3777). 2022-12-11 13:28:24 -05:00
Geza Lore 65e08f4dbf Make all expressions derive from AstNodeExpr (#3721).
Apart from the representational changes below, this patch renames
AstNodeMath to AstNodeExpr, and AstCMath to AstCExpr.

Now every expression (i.e.: those AstNodes that represent a [possibly
void] value, with value being interpreted in a very general sense) has
AstNodeExpr as a super class. This necessitates the introduction of an
AstStmtExpr, which represents an expression in statement position, e.g :
'foo();' would be represented as AstStmtExpr(AstCCall(foo)). In exchange
we can get rid of isStatement() in AstNodeStmt, which now really always
represent a statement

Peak memory consumption and verilation speed are not measurably changed.

Partial step towards #3420
2022-11-03 16:02:16 +00:00
Geza Lore 599d23697d
IEEE compliant scheduler (#3384)
This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278
2022-05-15 16:03:32 +01:00