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verilator
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2 Commits

Author SHA1 Message Date
Wilson Snyder 2aed499e00 Fix detecting missing reg types, bug1570. 2019-11-05 21:15:44 -05:00
Varun Koyyalagunta e0edb596ea Add duplicate clock gate optimization, msg980. 
Experimental and disabled unless -OD or -O3 used (for now),
Please try it as may get some significant speedups.

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
 2013-02-20 20:14:15 -05:00