Logo
Explore Help
Sign In
luke/verilator
Watch 1
Star 0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-07 10:33:13 +02:00
Code Issues Packages Projects Releases Wiki Activity
10,317 Commits 3 Branches 171 Tags
3fd16ed4983fcc97a1c96e1b9696b996df0243ab
Commit Graph
9 Commits
Author SHA1 Message Date
Artur Bieniek c9e3f59f26 Fix stale reads of continuously assigned forceable signals (#8223)
Signed-off-by: Artur Bieniek <[email protected]>
2026-09-15 21:15:37 -04:00
Geza Lore a07a980b73 Internals: Do not overload AstVar::isPrimaryIO() for sampled value vars 2026-06-15 09:17:41 +01:00
Wilson Snyder ed0506ea8d Internals: Use Var flag instead of magic names. No functional change intended. 2026-04-03 19:05:56 -04:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder 13327fa9c0 Copyright year update. 2026-01-01 07:22:09 -05:00
Wilson Snyder 46c7b69c64 Internals: UINFO now includes newline itself. No functional change. 2025-05-22 20:29:32 -04:00
Wilson Snyder cb1661f9d0 Internals: Cleanups (from parse branch). No functional change intended. 2025-04-27 14:17:24 -04:00
Wilson Snyder 8fbb725f34 Copyright year update. 2025-01-01 08:30:25 -05:00
Arkadiusz Kozdra 2cfec0ecc3 Support clocking blocks in virtual interfaces (#5235) 2024-07-09 18:31:58 -04:00
Powered by Gitea Version: 1.27.2 Page: 1101ms Template: 5ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API