Commit Graph

3 Commits

Author SHA1 Message Date
Geza Lore 599d23697d
IEEE compliant scheduler (#3384)
This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278
2022-05-15 16:03:32 +01:00
Wilson Snyder ac2058c7ec Tests: Fix t_unopt_combo_waive with -Oi 2020-11-25 21:18:13 -05:00
Stefan Wallentowitz 68a2ed6776
Fix output of loops on waiving (#2355)
When an unopt loop is waived, we also don't want the loop's example
path being plot.

Signed-off-by: Stefan Wallentowitz <stefan.wallentowitz@hm.edu>
2020-05-26 08:45:57 +02:00