Commit Graph

236 Commits

Author SHA1 Message Date
Bartłomiej Chmiel 31e73f1645
Support simple cycle delay sequence expressions inside assertion properties (#6508)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
2025-10-10 16:16:15 +02:00
Ryszard Rozak 09518ee207
Support aliases with more operands (#6501) 2025-09-29 13:23:51 -04:00
Geza Lore 603f4c615a
Improve Loop unrolling (#6480) (#6493)
This patch implements #6480. All loop statements are represented using
AstLoop and AstLoopTest.

This necessitates rework of the loop unroller to handle loops of
arbitrary form. To enable this, I have split the old unroller used for
'generate for' statements and moved it into V3Param, and subsequently
rewrote V3Unroll to handle the new representation. V3Unroll can now
unroll more complex loops, including with loop conditions containing
multiple variable references or inlined functions.

Handling the more generic code also requires some restrictions. If a
loop contains any of the following, it cannot be unrolled:
- A timing control that might suspend the loop
- A non-inlined call to a non-pure function

These constructs can change the values of variables in the loop, so are
generally not safe to unroll if they are present. (We could still unroll
if all the variables needed for unrolling are automatic, however we
don't do that right now.)

These restrictions seem ok in the benchmark suite, where the new
unroller can generally unroll many more loops than before.
2025-09-29 15:25:25 +01:00
Geza Lore 800af37975
Internals: Refactor generate construct Ast handling (#6280) (#6470)
Internals: Refactor generate construct Ast handling (#6280)

We introduce AstNodeGen, the common base class of AstGenBlock,
AstGenCase, AstGenFor, and AstGenIf, which together represent all SV
generate constructs. Subsequently remove AstNodeFor, AstNodeCase
(AstCase is now directly derived from AstNodeStmt) and adjust internals
to work on the new representation.

Output is identical modulo hashes do to changed AstNode type ids, no
functional change intended.

Step towards #6280.
2025-09-23 19:49:01 +01:00
Geza Lore 40ca0527db
Internal: Refactor AstAssignAlias (#6280) (#6473)
Rename AstAssignAlias to AstAlias and make it derive from AstNode
instead of AstNodeStmt.

Replace AstAlias with AstAssignW in V3LinkDot::linkDotScope, which is
the last place we need to be aware of the alias construct. Using
AstAssignW dowstream enables further optimization while preserving the
same functionality.
2025-09-22 16:30:26 -04:00
Geza Lore f39d6e6108
Deprecate sensitivity list on public_flat_rw attributes (#6443)
These are no longer required for correct scheduling. They are still
accepted for backward compatibility, but have no effect on simulation
and are dropped in the front-end. Also removed the then redundant
AstAlwaysPublic class.

Fixes #6442
2025-09-16 22:38:53 +01:00
Wilson Snyder 5f23bf95f6 Internals: Refactor V3EmitUtil to not be base class. No functional change. 2025-08-25 22:05:40 -04:00
Wilson Snyder ac2a75fbb5 Support future sampled value functions. 2025-08-23 21:16:53 -04:00
Geza Lore 636a6b8cd2
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.

Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).

The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.

V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.

The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.

V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.

Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 15:06:38 +01:00
Geza Lore 0bf9fc270f
Iternals: Remove AstAssignPre/AstAssignPost (#6307)
Replace with AstAlwaysPre/AstAlwaysPost with AstAssign under them.

Step towards #6280
2025-08-19 09:27:59 +01:00
Wilson Snyder 88046c8063 Internals: Rename AstSenTree pointers to sentreep. No functional change intended except JSON. 2025-08-17 19:14:34 -04:00
Geza Lore 6f69c990fd
Internals: Remove AstCondBound and AstNodeCond (#6293) (#6294)
Fixes #6293
2025-08-15 15:49:06 -07:00
Geza Lore d28436dccc
Fix stray ']' in Verilog code output for non-constant select (#6277) 2025-08-09 14:59:58 +01:00
Wilson Snyder 6a225d5d00 Internals: Remove AstSysFuncAsTask 2025-08-08 05:09:54 -04:00
Ryszard Rozak 7d2b6bd921
Internals: Optimize updates of Vtogcov signals. No functional change intended. (#6110) 2025-08-04 13:29:56 +01:00
Geza Lore 9d2adf3e49
Internals: Enable EmitV to output formatted code to std::ostream (#6239)
Introduce V3OutStream as a V3OutFormatter that writes to a stream
instead of a file. This can be used to emit formatted code fragments
e.g. in debug prints and graph dumps.
2025-07-30 13:41:21 +02:00
Geza Lore 7c5d462564
Remove AstJumpLabel (#6221)
Remove AstJumpLabel

AstJumpGo now references one if its enclosing AstJumpBlocks, and
branches straight after the referenced block.

That is:

```
JumpBlock a {
   ...
   JumpGo(a);
   ...
}
// <--- the JumpGo(a) goes here
```

This is sufficient for all use cases and makes control flow much easier to
reason about. As a result, V3Const can optimize a bit more aggressively.

Second half of, and fixes #6216
2025-07-23 17:51:16 +01:00
Geza Lore 763183f067
Internals: Remove AstWhile::precondsp() (#6219). No functional change intended. 2025-07-23 08:50:39 -04:00
Artur Bieniek abd509ce53
Support delays in emitted Verilog (#6177) 2025-07-16 11:52:56 -04:00
Wilson Snyder 73ca2ab997 Support `$past_gclk` 2025-07-01 18:00:04 -04:00
Geza Lore 916d473eff
Internals: Replace unnecessary AstSel::widthp() child node with const in node (#6117) 2025-06-24 11:59:09 -04:00
Wilson Snyder 46c7b69c64 Internals: UINFO now includes newline itself. No functional change. 2025-05-22 20:29:32 -04:00
Wilson Snyder 3b632739a8 Internals: Add RequireDType and check for recursive data types, in prep for future parser. 2025-05-17 20:40:03 -04:00
Todd Strader 7336b9ebfc
Add V3EmitV support for sampled value functions (#5931) 2025-04-11 12:25:56 -04:00
Wilson Snyder 53151d7c5f Fix emitting `this` (#5849) 2025-03-11 17:53:35 -04:00
Todd Strader f7ccc013e7
Improve V3EmitV for interfaces (#5796) 2025-02-21 16:49:14 -05:00
Todd Strader 70459b3208
Fix V3EmitV for non-zero based arrays (#5790) 2025-02-21 05:49:32 +11:00
Todd Strader b645fcf027
More V3EmitV support (#5779) 2025-02-14 14:58:11 -05:00
Wilson Snyder 929e15fa4c Fix various round-trip Verilog output, including packed arrays 2025-01-24 21:00:45 -05:00
Bartłomiej Chmiel 35fa0d051d
Support integer atom type ports in `--hierarchical` (#5748) 2025-01-24 07:47:11 -05:00
Wilson Snyder 8fbb725f34 Copyright year update. 2025-01-01 08:30:25 -05:00
Wilson Snyder a68da7e220 Internals: Style cleanup. Ignore whitespace if diff. No functional change. 2024-11-10 10:59:18 -05:00
Wilson Snyder 0fe8c73d19 Fix `$fatal` to not be affected by `+verilator+error+limit` (#5135). 2024-09-13 20:45:44 -04:00
Bartłomiej Chmiel a730daabef
Support 'parameter type' in hierarchical blocks (#5309) (#5333) 2024-08-21 05:30:59 -04:00
Bartłomiej Chmiel 4695967185
Fix signed types emitted in hierarchical Verilation (#5178)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
2024-06-14 08:07:32 -04:00
Wilson Snyder 22687a6901 Internals: Use C++14 quoted literal std::string 2024-01-28 21:00:20 -05:00
Wilson Snyder e76f29e5ba Copyright year update 2024-01-01 03:19:59 -05:00
Geza Lore ae6ec411d0 Remove dead code from V3EmitV 2023-11-02 20:25:44 +00:00
Aleksander Kiryk 83a0085c4d
Support `wait fork` (#4586) 2023-10-20 07:13:57 -04:00
Wilson Snyder b5828a7ce9 Fix header order botched by clang-format in recent commit. 2023-10-18 06:37:46 -04:00
github action 770cd24f27 Apply 'make format' 2023-10-18 02:50:27 +00:00
Wilson Snyder 431bb1ed16
Support compiling Verilator with gcc/clang precompiled headers (#4579) 2023-10-17 22:49:28 -04:00
Krzysztof Bieganski fb1fc46b06
Internals: Rework self pointers (#4396) 2023-09-08 07:34:35 -04:00
Ryszard Rozak e24197fd16
Don't move function calls before the expression (#4413) 2023-08-28 15:44:41 +02:00
Wilson Snyder 1069652701 Fix some AstExprStmt handling issues, towards side effect fixes. 2023-05-27 12:43:40 -04:00
Wilson Snyder f2aac8c49a Internals: Use VNVisitorConst where possible, for better performance. No functional change indended. 2023-03-18 12:23:17 -04:00
Wilson Snyder 9e25c21fed Fix unpacked struct clocking 2023-03-14 19:35:40 -04:00
Varun Koyyalagunta be26e8da1b
Support struct I/O in --lib-create (#3378) (#3892) 2023-01-22 22:24:36 -05:00
Wilson Snyder b24d7c83d3 Copyright year update 2023-01-01 10:18:39 -05:00
Wilson Snyder 833780fac1 Internal: cppcheck fixes. No functional change intended. 2022-11-27 05:52:40 -05:00