verilator

Commit Graph

Author	SHA1	Message	Date
Geza Lore	2e502aead8	Internals: Make all scheduling region use a single trigger vector. (#6620 ) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.	2025-11-01 15:43:20 +00:00
Geza Lore	59cb53cfbc	Set trigger vector in whole words (#5857 ) Having many triggers still hits a bottleneck in LLVM leading to long compile times. Instead of setting triggers bit-wise, set them as a whole 64-bit word when possible. This improves C++ compile times by ~4x on some large designs and has minor run-time performance benefit.	2025-03-14 14:06:51 +00:00

Author

SHA1

Message

Date

Geza Lore

2e502aead8

Internals: Make all scheduling region use a single trigger vector. (#6620 )

The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now
it uses a single "extended" trigger vector where the top bits are what
used to be the used bits in the 'pre' trigger vector. Please see the
description above `TriggerKit`. Also move the extra triggers from the
low end to the high end in the trigger vectors.

2025-11-01 15:43:20 +00:00

Geza Lore

59cb53cfbc

Set trigger vector in whole words (#5857 )

Having many triggers still hits a bottleneck in LLVM leading to long
compile times.

Instead of setting triggers bit-wise, set them as a whole 64-bit word
when possible. This improves C++ compile times by ~4x on some large
designs and has minor run-time performance benefit.

2025-03-14 14:06:51 +00:00

2 Commits