Commit Graph

4 Commits

Author SHA1 Message Date
Wilson Snyder 2c156d6655 Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change. 2025-12-20 21:46:43 -05:00
Geza Lore 7e55c62cac
Improve combinational cycle fixup in Dfg (#6744) (#6746)
Now that we have an efficient algorithm to analyse which bits in a
combinational cycle are not dependent on the cycle, can simplify the
cycle fixup algorithms. Remove FixUpSelDrivers: this was a heuristic
to save on the expensive independent bits analysis, but itself can
cause a performance problem on certain inputs that result in a large
number of attempted fixups. Doing this simplifies the driver tracing
algorithm, and because we now only attempt to trace drivers that are
known to be independent of the cycles, it should always succeed...
Unless of course there is a mismatch between the independent bit
analysis ant the driver tracing algorithm. In such case (when we managed
to prove independence, but then fail to trace a driver), we will crash,
which is still easier to sv-bugpoint than a performance bug.

Fixes #6744
2025-12-08 18:43:21 +00:00
Geza Lore 40ca0527db
Internal: Refactor AstAssignAlias (#6280) (#6473)
Rename AstAssignAlias to AstAlias and make it derive from AstNode
instead of AstNodeStmt.

Replace AstAlias with AstAssignW in V3LinkDot::linkDotScope, which is
the last place we need to be aware of the alias construct. Using
AstAssignW dowstream enables further optimization while preserving the
same functionality.
2025-09-22 16:30:26 -04:00
Geza Lore ce77bac99a
Break some combinational cycles in DFG (#6168)
Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:

```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```
2025-07-10 18:46:45 +01:00