Commit Graph

8 Commits

Author SHA1 Message Date
Andrew Nolte 18e317fb78
Fix inconsistent naming of generate scope arrays (#3840) 2023-02-01 17:30:02 -05:00
Todd Strader 12416bc0a3
Scope module fix (#2893) 2021-04-26 09:50:25 -04:00
Todd Strader 70c1eda174
Fix package reported as vpiModule (#2885) 2021-04-12 15:00:36 -04:00
Wilson Snyder 99afffa949 Tests: Add some verbose statements. 2021-02-03 19:38:44 -05:00
Wilson Snyder 153335ff35 Tests: Cleanup some DPI warnings. 2021-02-03 18:30:39 -05:00
Wilson Snyder 2b58e834ee Tests: Rename IVERILOG define for consistency. No functional change. 2020-04-23 08:05:14 -04:00
Wilson Snyder 1ce360ed5b Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
Stefan Wallentowitz 045ff25f80 Support vpiModule, bug1469.
Add very basic support for vpiModule. Basically it allows to traverse
the module tree to find a variable etc. It does not support more than
vpi_iterate and vpi_scan for vpiModule along basic operations like
vpi_get_str on vpiModule.

The support is added non-intrusively to non-VPI verilator runs. It
essentially:

 - Tracks the creation of cell instances and keeps them alive until
   the emit phase. They are there converted to scopes if modules.

 - Emits empty (don't add anything during construction)
   VerilatedScopes for all inlined modules, only for those inlined
   modules that are on the hierarchical path to public variables.

 - Adds VerilatedHierarchy as abstraction to structure of the
   scopes. It is only created for VPI designs. It allows to traverse
   the hierarchy from the top (NULL).

Signed-off-by: Stefan Wallentowitz <stefan@wallentowitz.de>
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
2019-10-01 21:57:45 -04:00