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verilator
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4 Commits

Author SHA1 Message Date
Wilson Snyder e238a2ca5e Verilog format 2026-02-22 13:50:01 -05:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder f3684a85b9 Fix delayed assignment malformed LHS assertion (#5904). 2025-03-30 17:38:54 -04:00
Wilson Snyder b49351356e Fix delays inside interface functions, and classes inside interfaces (#5846). 2025-03-30 16:40:22 -04:00