Merge branch 'master' into develop-v5

test_regress/t/t_public_clk.cpp

@@ -0,0 +1,41 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Todd Strader.
+// SPDX-License-Identifier: CC0-1.0
+
+// Generated header
+#include "Vt_public_clk.h"
+#include "Vt_public_clk___024root.h"
+// General headers
+#include "verilated.h"
+
+std::unique_ptr<Vt_public_clk> topp;
+int main(int argc, char** argv, char** env) {
+    vluint64_t sim_time = 1100;
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    contextp->commandArgs(argc, argv);
+    contextp->debug(0);
+    srand48(5);
+    topp.reset(new Vt_public_clk("top"));
+
+    topp->rootp->t__DOT__clk = 0;
+    topp->eval();
+    { contextp->timeInc(10); }
+
+    while ((contextp->time() < sim_time) && !contextp->gotFinish()) {
+        topp->rootp->t__DOT__clk = !topp->rootp->t__DOT__clk;
+        topp->eval();
+        contextp->timeInc(5);
+    }
+
+    if (!contextp->gotFinish()) {
+        vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
+    }
+    topp->final();
+
+    topp.reset();
+    return 0;
+}

test_regress/t/t_public_clk.pl

@@ -0,0 +1,27 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_flags2 => [
+        "--exe",
+        "$Self->{t_dir}/$Self->{name}.cpp"
+    ],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_public_clk.v

@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: public clock signal
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2022 by Todd Strader
+// SPDX-License-Identifier: CC0-1.0
+
+`ifdef VERILATOR
+// The '$c1(1)' is there to prevent inlining of the signal by V3Gate
+`define IMPURE_ONE ($c(1))
+`else
+// Use standard $random (chaces of getting 2 consecutive zeroes is zero).
+`define IMPURE_ONE (|($random | $random))
+`endif
+
+module t ();
+
+   logic clk /* verilator public_flat_rw */;
+   int count;
+   wire other_clk = `IMPURE_ONE & clk;
+
+   always_ff @(posedge other_clk) begin
+      count <= count + 1;
+      if (count == 10) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule

test_regress/t/t_public_seq.cpp

@@ -0,0 +1,45 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Todd Strader.
+// SPDX-License-Identifier: CC0-1.0
+
+// Generated header
+#include "Vt_public_seq.h"
+#include "Vt_public_seq___024root.h"
+// General headers
+#include "verilated.h"
+
+std::unique_ptr<Vt_public_seq> topp;
+int main(int argc, char** argv, char** env) {
+    vluint64_t sim_time = 1100;
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    contextp->commandArgs(argc, argv);
+    contextp->debug(0);
+    srand48(5);
+    topp.reset(new Vt_public_seq("top"));
+
+    topp->clk = 0;
+    topp->eval();
+    { contextp->timeInc(10); }
+
+    int cyc = 0;
+
+    while ((contextp->time() < sim_time) && !contextp->gotFinish()) {
+        if (cyc >= 5) ++topp->rootp->t__DOT__pub_byte;
+        topp->eval();
+        topp->clk = !topp->clk;
+        topp->eval();
+        contextp->timeInc(5);
+        if (topp->clk) cyc++;
+    }
+    if (!contextp->gotFinish()) {
+        vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
+    }
+    topp->final();
+
+    topp.reset();
+    return 0;
+}

test_regress/t/t_public_seq.pl

@@ -0,0 +1,27 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_flags2 => [
+        "--exe",
+        "$Self->{t_dir}/$Self->{name}.cpp"
+    ],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_public_seq.v

@@ -0,0 +1,42 @@
+// DESCRIPTION: Verilator: public clock signal
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2022 by Todd Strader
+// SPDX-License-Identifier: CC0-1.0
+
+`ifdef VERILATOR
+// The '$c1(1)' is there to prevent inlining of the signal by V3Gate
+`define IMPURE_ONE ($c(1))
+`else
+// Use standard $random (chaces of getting 2 consecutive zeroes is zero).
+`define IMPURE_ONE (|($random | $random))
+`endif
+
+module t (
+   input clk,
+   input dummy_clk // Never toggled from C++
+);
+
+   int count;
+
+   logic [7:0] pub_byte /* verilator public_flat_rw */ = 123;
+   logic [7:0] comb_byte;
+
+   always_comb comb_byte = `IMPURE_ONE ? pub_byte : '0;
+
+   always_ff @(posedge clk) begin
+      count <= count + 1;
+      if (comb_byte != pub_byte) begin
+         $display("%%Error: comb_byte (%0d) != pub_byte (%0d)", comb_byte, pub_byte);
+         $stop;
+      end
+      if (count == 10) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+   always_ff @(posedge dummy_clk) begin
+      comb_byte = ~pub_byte;
+   end
+endmodule