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Tests: Fix race and dead code.

This commit is contained in:
Wilson Snyder 2018-05-05 07:44:11 -04:00
parent c8ba51581f
commit ff61bb509c
5 changed files with 11 additions and 18 deletions
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4
test_regress/t/t_case_write1.v
View File

@ -14,6 +14,7 @@ module t (/*AUTOARG*/
reg [63:0] crc;
`verilator_file_descriptor fd;
`verilator_file_descriptor fdtmp;
t_case_write1_tasks tasks ();
@ -32,7 +33,8 @@ module t (/*AUTOARG*/
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("Open obj_dir/t_case_write1/t_case_write1_logger.log\n");
fd = $fopen("obj_dir/t_case_write1/t_case_write1_logger.log", "w");
fdtmp = $fopen("obj_dir/t_case_write1/t_case_write1_logger.log", "w");
fd <= fdtmp;
end
if (cyc==90) begin
$write("*-* All Finished *-*\n");

4
test_regress/t/t_case_write2.v
View File

@ -14,6 +14,7 @@ module t (/*AUTOARG*/
reg [63:0] crc;
`verilator_file_descriptor fd;
`verilator_file_descriptor fdtmp;
t_case_write2_tasks tasks ();
@ -32,7 +33,8 @@ module t (/*AUTOARG*/
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("Open obj_dir/t_case_write2/t_case_write2_logger.log\n");
fd = $fopen("obj_dir/t_case_write2/t_case_write2_logger.log", "w");
fdtmp = $fopen("obj_dir/t_case_write2/t_case_write2_logger.log", "w");
fd <= fdtmp;
end
if (cyc==90) begin
$write("*-* All Finished *-*\n");

2
test_regress/t/t_dist_fixme.pl
View File

@ -19,7 +19,7 @@ if (!-r "$root/.git") {
my $files = `cd $root && git ls-files --exclude-standard`;
print "ST $files\n" if $Debug;
$files =~ s/\s+/ /g;
my $cmd = "cd $root && fgrep -n FIX"."ME $files | sort | grep -v t_dist_fixme";
my $cmd = "cd $root && grep -n -P '(FIX"."ME|BO"."ZO)' $files | sort";
my $grep = `$cmd`;
print "$grep\n";
if ($grep ne "") {

6
test_regress/t/t_func_endian.pl
View File

@ -8,11 +8,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
compile (
);
);
execute (
check_finished=>1,
);
check_finished=>1,
);
ok(1);
1;

13
test_regress/t/t_func_endian.v
View File

@ -21,13 +21,11 @@ module t (/*AUTOARG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [31:0] swapped; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
.swapped (swapped[31:0]),
// Inputs
.clk (clk),
.noswap (noswap),
@ -67,7 +65,7 @@ endmodule
module Test (/*AUTOARG*/
// Outputs
out, swapped,
out,
// Inputs
clk, noswap, nibble, in
);
@ -78,7 +76,6 @@ module Test (/*AUTOARG*/
input [31:0] in;
output [31:0] out;
output [31:0] swapped;
function [7:0] EndianSwap;
input Nibble;
@ -98,12 +95,4 @@ module Test (/*AUTOARG*/
: EndianSwap(nibble, in[15:8]));
assign out[7:0] = (noswap ? in[7:0]
: EndianSwap(nibble, in[7:0]));
reg [31:0] swapped;
always @(posedge clk) begin
swapped[31:24] <= EndianSwap(nibble, in[31:24]);
swapped[23:16] <= EndianSwap(nibble, in[23:16]);
swapped[15:8] <= EndianSwap(nibble, in[15:8] );
swapped[7:0] <= EndianSwap(nibble, in[7:0] );
end
endmodule