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verilator
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This commit is contained in:
Wilson Snyder 2020-05-10 11:01:57 -04:00
parent 6e7ee23644
commit feb1e2bd48
2 changed files with 7 additions and 0 deletions
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6
src/verilog.y
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@ -1971,6 +1971,8 @@ type_declaration<nodep>: // ==IEEE: type_declaration
| yTYPEDEF id/*interface*/ '.' idAny/*type*/ idAny/*type*/ ';' { $$ = NULL; BBUNSUP($1, "Unsupported: SystemVerilog 2005 typedef in this context"); }
// // Combines into above "data_type id" rule
// // Verilator: Not important what it is in the AST, just need to make sure the yaID__aTYPE gets returned
//UNSUP // Below should be idAny to allow duplicate forward defs; need to expand
// // data_type to exclude IDs, or add id__SEMI rule
| yTYPEDEF id ';' { $$ = NULL; $$ = new AstTypedefFwd($<fl>2, *$2); SYMP->reinsert($$); PARSEP->tagNodep($$); }
| yTYPEDEF yENUM idAny ';' { $$ = NULL; $$ = new AstTypedefFwd($<fl>3, *$3); SYMP->reinsert($$); PARSEP->tagNodep($$); }
| yTYPEDEF ySTRUCT idAny ';' { $$ = NULL; $$ = new AstTypedefFwd($<fl>3, *$3); SYMP->reinsert($$); PARSEP->tagNodep($$); }
@ -4267,6 +4269,8 @@ gateRangeE<nodep>:
gateBuf<nodep>:
gateFront variable_lvalue ',' gatePinExpr ')'
{ $$ = new AstAssignW($<fl>1, $2, $4); DEL($1); }
// UNSUP // IEEE: Multiple output variable_lvalues
// UNSUP // Causes conflict - need to take in variable_lvalue or a gatePinExpr
;
gateBufif0<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
@ -4279,6 +4283,8 @@ gateBufif1<nodep>:
gateNot<nodep>:
gateFront variable_lvalue ',' gatePinExpr ')'
{ $$ = new AstAssignW($<fl>1, $2, new AstNot($<fl>1, $4)); DEL($1); }
// UNSUP // IEEE: Multiple output variable_lvalues
// UNSUP // Causes conflict - need to take in variable_lvalue or a gatePinExpr
;
gateNotif0<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'

1
test_regress/t/t_typedef.v
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@ -8,6 +8,7 @@ program t;
parameter SIZE = 5;
typedef vec_t; // Forward
//UNSUP typedef vec_t; // Multi-forward is ok
typedef reg [SIZE-1:0] vec_t ;
vec_t a; initial a =0;