luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 01:54:01 +02:00
Code Issues Packages Projects Releases Wiki Activity

Internals: Progress towards proper short-circuit evaluation

Browse Source
This commit is contained in:
Wilson Snyder
2011-12-22 08:33:16 -05:00
parent 76232cd9e7
commit fdeb6bcae0
4 changed files with 115 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/V3Slice.cpp
+2 -2
View File
@@ -161,10 +161,10 @@ class SliceCloneVisitor : public AstNVisitor {
if (lhsp && rhsp) {
switch (redOpType) {
case REDOP_OR:
lhsp = new AstLogOr(nodep->fileline(), lhsp, rhsp);
lhsp = new AstOr(nodep->fileline(), lhsp, rhsp);
break;
case REDOP_AND:
lhsp = new AstLogAnd(nodep->fileline(), lhsp, rhsp);
lhsp = new AstAnd(nodep->fileline(), lhsp, rhsp);
break;
case REDOP_XOR:
lhsp = new AstXor(nodep->fileline(), lhsp, rhsp);