Add support

Changes

@@ -5,7 +5,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.66*
 
-***  Support $feof.  [Holger Waechtler]
+***  Support $feof, $fflush.  [Holger Waechtler]
 
 * Verilator 3.665 2008/06/25
 

bin/verilator

@@ -1554,7 +1554,7 @@ them with a $write with the appropriate format specifier.
 
 The rarely used optional parameter to $finish and $stop is ignored.
 
-=item $fopen, $fclose, $fdisplay, $feof, $fwrite
+=item $fopen, $fclose, $fdisplay, $feof, $fflush, $fwrite
 
 File descriptors passed to the file PLI calls must be file descriptors, not
 MCDs, which includes the mode parameter to $fopen being mandatory.

src/V3AstNodes.h

@@ -1323,6 +1323,29 @@ struct AstFOpen : public AstNodeStmt {
     AstNode*	modep() const { return op3p(); }
 };
 
+struct AstFFlush : public AstNodeStmt {
+    // Parents: stmtlist
+    // Children: file which must be a varref
+    AstFFlush(FileLine* fileline, AstNode* filep)
+	: AstNodeStmt (fileline) {
+	setNOp2p(filep);
+    }
+    virtual ~AstFFlush() {}
+    virtual AstType type() const { return AstType::FFLUSH;}
+    virtual AstNode* clone() { return new AstFFlush(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual string verilogKwd() const { return "$fflush"; };
+    virtual bool isGateOptimizable() const { return false; }
+    virtual bool isPredictOptimizable() const { return false; }
+    virtual bool isSplittable() const { return false; }
+    virtual bool isOutputter() const { return true; }
+    virtual bool isUnlikely() const { return true; }
+    virtual V3Hash sameHash() const { return V3Hash(); }
+    virtual bool same(AstNode* samep) const { return true; }
+    AstNode*	filep() const { return op2p(); }
+    void filep(AstNodeVarRef* nodep) { setNOp2p(nodep); }
+};
+
 struct AstReadMem : public AstNodeStmt {
 private:
     bool	m_isHex;	// readmemh, not readmemb

src/V3EmitC.cpp

@@ -299,6 +299,13 @@ public:
 	nodep->filep()->iterateAndNext(*this);
 	puts(")) : true)"); // Non-existant filehandle should return EOF
     }
+    virtual void visit(AstFFlush* nodep, AstNUser*) {
+	puts("if (");
+	nodep->filep()->iterateAndNext(*this);
+	puts(") { fflush (VL_CVT_Q_FP(");
+	nodep->filep()->iterateAndNext(*this);
+	puts(")); ");
+    }
     virtual void visit(AstWhile* nodep, AstNUser*) {
 	nodep->precondsp()->iterateAndNext(*this);
 	puts("while (");

src/V3EmitV.cpp

@@ -192,6 +192,12 @@ public:
 	if (nodep->filep()) nodep->filep()->iterateChildren(*this);
 	puts(");\n");
     }
+    virtual void visit(AstFFlush* nodep, AstNUser*) {
+	putbs(nodep->verilogKwd());
+	putbs(" (");
+	if (nodep->filep()) nodep->filep()->iterateChildren(*this);
+	puts(");\n");
+    }
     virtual void visit(AstReadMem* nodep, AstNUser*) {
 	putbs(nodep->verilogKwd());
 	putbs(" (");

src/V3LinkLValue.cpp

@@ -108,6 +108,14 @@ private:
 	}
 	m_setRefLvalue = last_setRefLvalue;
     }
+    virtual void visit(AstFFlush* nodep, AstNUser*) {
+	bool last_setRefLvalue = m_setRefLvalue;
+	{
+	    m_setRefLvalue = true;
+	    nodep->filep()->iterateAndNext(*this);
+	}
+	m_setRefLvalue = last_setRefLvalue;
+    }
     virtual void visit(AstReadMem* nodep, AstNUser*) {
 	bool last_setRefLvalue = m_setRefLvalue;
 	{

src/V3LinkResolve.cpp

@@ -328,6 +328,10 @@ private:
 	nodep->iterateChildren(*this);
 	expectDescriptor(nodep, nodep->filep()->castNodeVarRef());
     }
+    virtual void visit(AstFFlush* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+	expectDescriptor(nodep, nodep->filep()->castNodeVarRef());
+    }
     virtual void visit(AstDisplay* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
 	if (nodep->filep()) expectDescriptor(nodep, nodep->filep()->castNodeVarRef());

src/V3Width.cpp

@@ -574,6 +574,9 @@ private:
 	nodep->lhsp()->iterateAndNext(*this,WidthVP(64,64,BOTH).p());
 	nodep->width(1,1);
     }
+    virtual void visit(AstFFlush* nodep, AstNUser*) {
+	nodep->filep()->iterateAndNext(*this,WidthVP(64,64,BOTH).p());
+    }
     virtual void visit(AstReadMem* nodep, AstNUser*) {
 	nodep->filenamep()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
 	nodep->memp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());

src/verilog.l

@@ -133,6 +133,7 @@ escid	\\[^ \t\f\r\n]+
   "$fclose"		{yylval.fileline = CRELINE(); return yD_FCLOSE;}
   "$fdisplay"		{yylval.fileline = CRELINE(); return yD_FDISPLAY;}
   "$feof"		{yylval.fileline = CRELINE(); return yD_FEOF;}
+  "$fflush"		{yylval.fileline = CRELINE(); return yD_FFLUSH;}
   "$finish"		{yylval.fileline = CRELINE(); return yD_FINISH;}
   "$fopen"		{yylval.fileline = CRELINE(); return yD_FOPEN;}
   "$fullskew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}

src/verilog.y

@@ -227,6 +227,7 @@ class AstSenTree;
 %token<fileline>	yD_FCLOSE	"$fclose"
 %token<fileline>	yD_FDISPLAY	"$fdisplay"
 %token<fileline>	yD_FEOF		"$feof"
+%token<fileline>	yD_FFLUSH	"$fflush"
 %token<fileline>	yD_FINISH	"$finish"
 %token<fileline>	yD_FOPEN	"$fopen"
 %token<fileline>	yD_FWRITE	"$fwrite"
@@ -896,6 +897,9 @@ stmt:		';'					{ $$ = NULL; }
 	|	'{' concIdList '}' '=' delayE expr ';'  { $$ = new AstAssign($4,$2,$6); }
 	|	yD_C '(' cStrList ')' ';'		{ $$ = (v3Global.opt.ignc() ? NULL : new AstUCStmt($1,$3)); }
 	|	yD_FCLOSE '(' varRefDotBit ')' ';'	{ $$ = new AstFClose($1, $3); }
+	|	yD_FFLUSH ';'				{ $1->v3error("Unsupported: $fflush of all handles does not map to C++.\n"); }
+	|	yD_FFLUSH '(' ')' ';'			{ $1->v3error("Unsupported: $fflush of all handles does not map to C++.\n"); }
+	|	yD_FFLUSH '(' varRefDotBit ')' ';'	{ $$ = new AstFClose($1, $3); }
 	|	yD_FINISH parenE ';'			{ $$ = new AstFinish($1); }
 	|	yD_FINISH '(' expr ')' ';'		{ $$ = new AstFinish($1); }
 	|	yD_STOP parenE ';'			{ $$ = new AstStop($1); }

test_regress/t/t_sys_file.v

@@ -21,6 +21,7 @@ module t;
 
       $fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667);
       $fwrite(file, "[%0t] %s\n", $time, "Hello2");
+      $fflush(file);
 
       $fclose(file);
 `ifdef verilator