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Add --bbox-sys option to blackbox $system calls.

This commit is contained in:
Wilson Snyder 2009-09-16 09:28:09 -04:00
parent 4c7b5005a6
commit faa5ef193b
9 changed files with 85 additions and 19 deletions
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2
Changes
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@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.7***
** Add --bbox-sys option to blackbox $system calls.
*** Improved warning when "do" used as identifier.
**** Fix tracing escaped dotted identifiers, bug107.

19
bin/verilator
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@ -179,6 +179,7 @@ descriptions in the next sections for more information.
--assert Enable all assertions
--autoflush Flush streams after all $displays
--bbox-sys Blackbox unknown $system calls
--bin <filename> Override Verilator binary
--cc Create C++ output
--compiler <compiler-name> Tune for specified C++ compiler
@ -193,7 +194,7 @@ descriptions in the next sections for more information.
--debugi-<srcfile> <level> Enable debugging a source file at a level
--dump-tree Enable dumping .tree files
-E Preprocess, but do not compile
--error-limit <value> Abort after this number of errors
--error-limit <value> Abort after this number of errors
--exe Link to create executable
-f <file> Parse options from a file
--help Display this help.
@ -228,11 +229,14 @@ descriptions in the next sections for more information.
--trace-depth <levels> Depth of tracing
-U<var> Undefine preprocessor define
--underline-zero Zero signals with leading _'s
-V Verbose version and config
--unroll-count <loops> Tune maximum loop iterations
--unroll-stmts <stmts> Tune maximum loop body size
-V Verbose version and config
-v <filename> Verilog library
-Werror-<message> Convert warning to error
-Wfuture-<message> Disable unknown message warnings
-Wno-<message> Disable warning
-Wno-lint Disable all lint warnings
-x-assign <mode> Initially assign Xs to this value
-y <dir> Directory to search for modules
@ -269,6 +273,14 @@ After every $display or $fdisplay, flush the output stream. This insures
that messages will appear immediately but may reduce performance. Defaults
off, which will buffer output as provided by the normal C stdio calls.
=item --bbox-sys
Black box any unknown $system task or function calls. System tasks will be
simply NOPed, and system functions will be replaced by unsized zero.
Arguments to such functions will be parsed, but not otherwise checked.
This prevents errors when linting in the presence of company specific PLI
calls.
=item --bin I<filename>
Rarely needed. Override the default filename for Verilator itself. When a
@ -441,6 +453,9 @@ appropriate `begin_keywords.
Check the files for lint violations only, do not create any other output.
If the design is not to be completely Verilated see also the --bbox-sys
option.
=item --MMD
Enable creation of .d dependency files, used for make dependency detection,

1
src/V3Options.cpp
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@ -638,6 +638,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
else if ( onoff (sw, "-MP", flag/*ref*/) ) { m_makePhony = flag; }
else if ( onoff (sw, "-assert", flag/*ref*/) ) { m_assert = flag; m_psl = flag; }
else if ( onoff (sw, "-autoflush", flag/*ref*/) ) { m_autoflush = flag; }
else if ( onoff (sw, "-bbox-sys", flag/*ref*/) ) { m_bboxSys = flag; }
else if ( !strcmp (sw, "-cc") ) { m_outFormatOk = true; m_systemC = false; m_systemPerl = false; }
else if ( onoff (sw, "-coverage", flag/*ref*/) ) { coverage(flag); }
else if ( onoff (sw, "-coverage-line", flag/*ref*/) ){ m_coverageLine = flag; }

2
src/V3Options.h
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@ -94,6 +94,7 @@ class V3Options {
bool m_makePhony; // main switch: -MP
bool m_assert; // main switch: --assert
bool m_autoflush; // main switch: --autoflush
bool m_bboxSys; // main switch: --bbox-sys
bool m_coverageLine; // main switch: --coverage-block
bool m_coverageToggle;// main switch: --coverage-toggle
bool m_coverageUser; // main switch: --coverage-func
@ -204,6 +205,7 @@ class V3Options {
bool stats() const { return m_stats; }
bool assertOn() const { return m_assert; } // assertOn as __FILE__ may be defined
bool autoflush() const { return m_autoflush; }
bool bboxSys() const { return m_bboxSys; }
bool coverage() const { return m_coverageLine || m_coverageToggle || m_coverageUser; }
bool coverageLine() const { return m_coverageLine; }
bool coverageToggle() const { return m_coverageToggle; }

30
src/verilog.l
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@ -44,6 +44,10 @@ extern void yyerrorf(const char* format, ...);
#define FL { yylval.fileline = CRELINE(); }
#define RETURN_BBOX_SYS_OR_MSG(msg,yytext) { \
if (v3Global.opt.bboxSys()) return yD_aIGNORE; \
else yyerrorf(msg,yytext); }
void V3Read::ppline (const char* textp) {
// Handle `line directive
fileline()->lineDirective(textp);
@ -239,18 +243,18 @@ escid \\[^ \t\f\r\n]+
"xnor" { FL; return yXNOR; }
"xor" { FL; return yXOR; }
/* Special errors */
"$displayb" { yyerrorf("Unsupported: Use $display with %%b format instead: %s",yytext); }
"$displayh" { yyerrorf("Unsupported: Use $display with %%x format instead: %s",yytext); }
"$displayo" { yyerrorf("Unsupported: Use $display with %%o format instead: %s",yytext); }
"$fdisplayb" { yyerrorf("Unsupported: Use $fdisplay with %%b format instead: %s",yytext); }
"$fdisplayh" { yyerrorf("Unsupported: Use $fdisplay with %%x format instead: %s",yytext); }
"$fdisplayo" { yyerrorf("Unsupported: Use $fdisplay with %%o format instead: %s",yytext); }
"$fwriteb" { yyerrorf("Unsupported: Use $fwrite with %%b format instead: %s",yytext); }
"$fwriteh" { yyerrorf("Unsupported: Use $fwrite with %%x format instead: %s",yytext); }
"$fwriteo" { yyerrorf("Unsupported: Use $fwrite with %%o format instead: %s",yytext); }
"$writeb" { yyerrorf("Unsupported: Use $write with %%b format instead: %s",yytext); }
"$writeh" { yyerrorf("Unsupported: Use $write with %%x format instead: %s",yytext); }
"$writeo" { yyerrorf("Unsupported: Use $write with %%o format instead: %s",yytext); }
"$displayb" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $display with %%b format instead: %s",yytext); }
"$displayh" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $display with %%x format instead: %s",yytext); }
"$displayo" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $display with %%o format instead: %s",yytext); }
"$fdisplayb" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fdisplay with %%b format instead: %s",yytext); }
"$fdisplayh" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fdisplay with %%x format instead: %s",yytext); }
"$fdisplayo" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fdisplay with %%o format instead: %s",yytext); }
"$fwriteb" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fwrite with %%b format instead: %s",yytext); }
"$fwriteh" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fwrite with %%x format instead: %s",yytext); }
"$fwriteo" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $fwrite with %%o format instead: %s",yytext); }
"$writeb" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%b format instead: %s",yytext); }
"$writeh" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%x format instead: %s",yytext); }
"$writeo" { RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%o format instead: %s",yytext); }
/* Generic unsupported warnings */
"cmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"deassign" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
@ -461,7 +465,7 @@ escid \\[^ \t\f\r\n]+
/* Default PLI rule */
<V95,V01,V05,S05,PSL>{
"$"[a-zA-Z_$][a-zA-Z0-9_$]* { yyerrorf("Unsupported or unknown PLI call: %s",yytext); }
"$"[a-zA-Z_$][a-zA-Z0-9_$]* { FL; RETURN_BBOX_SYS_OR_MSG("Unsupported or unknown PLI call: %s",yytext); }
}
/************************************************************************/

11
src/verilog.y
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@ -327,6 +327,7 @@ class AstSenTree;
%token<fileline> yD_UNSIGNED "$unsigned"
%token<fileline> yD_WARNING "$warning"
%token<fileline> yD_WRITE "$write"
%token<fileline> yD_aIGNORE "${ignored-bbox-sys}"
%token<fileline> yPSL "psl"
%token<fileline> yPSL_ASSERT "PSL assert"
@ -1663,7 +1664,10 @@ function_subroutine_callNoMethod<nodep>: // IEEE: function_subroutine_call (as f
system_t_call<nodep>: // IEEE: system_tf_call (as task)
//
yD_C '(' cStrList ')' { $$ = (v3Global.opt.ignc() ? NULL : new AstUCStmt($1,$3)); }
yD_aIGNORE '(' ')' { $$ = NULL; }
| yD_aIGNORE '(' exprList ')' { $$ = NULL; }
//
| yD_C '(' cStrList ')' { $$ = (v3Global.opt.ignc() ? NULL : new AstUCStmt($1,$3)); }
| yD_FCLOSE '(' idClassSel ')' { $$ = new AstFClose($1, $3); }
| yD_FFLUSH { $1->v3error("Unsupported: $fflush of all handles does not map to C++.\n"); }
| yD_FFLUSH '(' ')' { $1->v3error("Unsupported: $fflush of all handles does not map to C++.\n"); }
@ -1697,7 +1701,10 @@ system_t_call<nodep>: // IEEE: system_tf_call (as task)
;
system_f_call<nodep>: // IEEE: system_tf_call (as func)
yD_BITS '(' expr ')' { $$ = new AstAttrOf($1,AstAttrType::BITS,$3); }
yD_aIGNORE '(' ')' { $$ = new AstConst($1,V3Number($1,0,0)); } // Unsized 0
| yD_aIGNORE '(' exprList ')' { $$ = new AstConst($1,V3Number($1,0,0)); } // Unsized 0
//
| yD_BITS '(' expr ')' { $$ = new AstAttrOf($1,AstAttrType::BITS,$3); }
| yD_C '(' cStrList ')' { $$ = (v3Global.opt.ignc() ? NULL : new AstUCFunc($1,$3)); }
| yD_CLOG2 '(' expr ')' { $$ = new AstCLog2($1,$3); }
| yD_COUNTONES '(' expr ')' { $$ = new AstCountOnes($1,$3); }

6
test_regress/Makefile
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@ -24,11 +24,13 @@ include $(VERILATOR_ROOT)/include/verilated.mk
######################################################################
ifneq ($(VCS_HOME),)
PRODUCTS += --vcs
#Default to off, even with vcs; not all tests are insured to be working
#PRODUCTS += --vcs
endif
ifneq ($(NC_ROOT),)
PRODUCTS += --nc
#Default to off, even with vcs; not all tests are insured to be working
#PRODUCTS += --nc
endif
PRODUCTS += --v3

19
test_regress/t/t_flag_bboxsys.pl Executable file
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@ -0,0 +1,19 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
v_flags2 => ["--bbox-sys"],
) if $Self->{v3};
execute (
check_finished=>1,
) if $Self->{v3};
ok(1);
1;

14
test_regress/t/t_flag_bboxsys.v Normal file
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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module a;
reg a;
initial begin
$unknown_sys_task_call_to_be_bbox("blah");
a = $unknown_sys_func_call(23);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule