Internals: Format CITATION.cff as proper YAML

This commit is contained in:
Wilson Snyder 2025-12-20 22:19:15 -05:00
parent a64b083b2a
commit fa99e7b697
2 changed files with 6 additions and 4 deletions

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@ -1,3 +1,4 @@
---
# See https://citation-file-format.github.io/ # See https://citation-file-format.github.io/
cff-version: 1.2.0 cff-version: 1.2.0
title: Verilator title: Verilator
@ -14,14 +15,14 @@ authors:
family-names: Wasson family-names: Wasson
- given-names: Duane - given-names: Duane
family-names: Galbi family-names: Galbi
- given-names: Geza
family-names: Lore
- name: 'et al' - name: 'et al'
repository-code: 'https://github.com/verilator/verilator' repository-code: 'https://github.com/verilator/verilator'
url: 'https://verilator.org' url: 'https://verilator.org'
abstract: >- abstract: >-
The Verilator package converts Verilog and SystemVerilog hardware The Verilator package converts Verilog and SystemVerilog hardware
description language (HDL) designs into a fast C++ or SystemC model description language (HDL) designs into a fast C++ or SystemC model
that, after compiling, can be executed. Verilator is not a that, after compiling, can be executed. Verilator is not only a
traditional simulator but a compiler. traditional simulator but a compiler.
license: license: [LGPL-3.0-only, Artistic-2.0]
- LGPL-3.0-only
- Artistic-2.0

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@ -541,6 +541,7 @@ YAML_FILES = \
.*.yml \ .*.yml \
.github/*.yml \ .github/*.yml \
.github/*/*.yml \ .github/*/*.yml \
CITATION.cff \
###################################################################### ######################################################################
# Format # Format