Internals: Format CITATION.cff as proper YAML
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---
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# See https://citation-file-format.github.io/
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# See https://citation-file-format.github.io/
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cff-version: 1.2.0
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cff-version: 1.2.0
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title: Verilator
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title: Verilator
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@ -14,14 +15,14 @@ authors:
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family-names: Wasson
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family-names: Wasson
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- given-names: Duane
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- given-names: Duane
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family-names: Galbi
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family-names: Galbi
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- given-names: Geza
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family-names: Lore
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- name: 'et al'
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- name: 'et al'
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repository-code: 'https://github.com/verilator/verilator'
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repository-code: 'https://github.com/verilator/verilator'
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url: 'https://verilator.org'
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url: 'https://verilator.org'
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abstract: >-
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abstract: >-
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The Verilator package converts Verilog and SystemVerilog hardware
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The Verilator package converts Verilog and SystemVerilog hardware
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description language (HDL) designs into a fast C++ or SystemC model
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description language (HDL) designs into a fast C++ or SystemC model
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that, after compiling, can be executed. Verilator is not a
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that, after compiling, can be executed. Verilator is not only a
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traditional simulator but a compiler.
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traditional simulator but a compiler.
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license:
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license: [LGPL-3.0-only, Artistic-2.0]
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- LGPL-3.0-only
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- Artistic-2.0
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@ -541,6 +541,7 @@ YAML_FILES = \
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.*.yml \
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.*.yml \
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.github/*.yml \
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.github/*.yml \
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.github/*/*.yml \
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.github/*/*.yml \
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CITATION.cff \
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######################################################################
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######################################################################
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# Format
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# Format
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