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verilator
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Internals: Detab and fix spacing style issues in tests and scripts. No functional change.

This commit is contained in:
Wilson Snyder 2019-05-07 22:34:09 -04:00
parent 37c8cc82b2
commit f818ddc71c
77 changed files with 3109 additions and 3102 deletions
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10
bin/verilator
View File

@ -58,7 +58,7 @@ foreach my $sw (@ARGV) {
} }
Getopt::Long::config("no_auto_abbrev","pass_through"); Getopt::Long::config("no_auto_abbrev","pass_through");
if (! GetOptions ( if (! GetOptions(
# Major operating modes # Major operating modes
"help" => \&usage, "help" => \&usage,
"debug:s" => \&debug, "debug:s" => \&debug,
@ -2082,7 +2082,7 @@ command line, or the link), you'd then:
#include "svdpi.h" #include "svdpi.h"
#include "Vour__Dpi.h" #include "Vour__Dpi.h"
int add (int a, int b) { return a+b; } int add(int a, int b) { return a+b; }
=head2 DPI System Task/Functions =head2 DPI System Task/Functions
@ -2132,7 +2132,7 @@ respect to that top level module, then the scope could be set with
#include "svdpi.h" #include "svdpi.h"
... ...
svSetScope (svGetScopeFromName ("dut")); svSetScope(svGetScopeFromName("dut"));
(Remember that Verilator adds a "V" to the top of the module hierarchy.) (Remember that Verilator adds a "V" to the top of the module hierarchy.)
@ -2146,7 +2146,7 @@ comments within the svdpi.h header for more information.
Verilator allows writing $display like functions using this syntax: Verilator allows writing $display like functions using this syntax:
import "DPI-C" function void import "DPI-C" function void
\$my_display (input string formatted /*verilator sformat*/ ); \$my_display(input string formatted /*verilator sformat*/ );
The /*verilator sformat*/ indicates that this function accepts a $display The /*verilator sformat*/ indicates that this function accepts a $display
like format specifier followed by any number of arguments to satisfy the like format specifier followed by any number of arguments to satisfy the
@ -2254,7 +2254,7 @@ accesses the above signal "readme" would be:
#include "verilated_vpi.h" // Required to get definitions #include "verilated_vpi.h" // Required to get definitions
vluint64_t main_time = 0; // See comments in first example vluint64_t main_time = 0; // See comments in first example
double sc_time_stamp () { return main_time; } double sc_time_stamp() { return main_time; }
void read_and_check() { void read_and_check() {
vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL); vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);

2
bin/verilator_difftree
View File

@ -38,7 +38,7 @@ my $Opt_Lineno = 1;
autoflush STDOUT 1; autoflush STDOUT 1;
autoflush STDERR 1; autoflush STDERR 1;
Getopt::Long::config("no_auto_abbrev"); Getopt::Long::config("no_auto_abbrev");
if (! GetOptions ( if (! GetOptions(
"help" => \&usage, "help" => \&usage,
"debug" => \&debug, "debug" => \&debug,
"<>" => \&parameter, "<>" => \&parameter,

2
bin/verilator_profcfunc
View File

@ -24,7 +24,7 @@ my $Opt_File;
autoflush STDOUT 1; autoflush STDOUT 1;
autoflush STDERR 1; autoflush STDERR 1;
Getopt::Long::config("no_auto_abbrev"); Getopt::Long::config("no_auto_abbrev");
if (! GetOptions ( if (! GetOptions(
"help" => \&usage, "help" => \&usage,
"debug" => \&debug, "debug" => \&debug,
"<>" => \&parameter, "<>" => \&parameter,

4
examples/tracing_c/sim_main.cpp
View File

@ -94,11 +94,11 @@ int main(int argc, char** argv, char** env) {
#if VM_TRACE #if VM_TRACE
// Dump trace data for this cycle // Dump trace data for this cycle
if (tfp) tfp->dump (main_time); if (tfp) tfp->dump(main_time);
#endif #endif
// Read outputs // Read outputs
VL_PRINTF ("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x" VL_PRINTF("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
" -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n", " -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n",
main_time, top->clk, top->reset_l, top->in_quad, main_time, top->clk, top->reset_l, top->in_quad,
top->out_quad, top->out_wide[2], top->out_wide[1], top->out_wide[0]); top->out_quad, top->out_wide[2], top->out_wide[1], top->out_wide[0]);

2
examples/tracing_sc/sub.v
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@ -49,7 +49,7 @@ module sub
// An example assertion // An example assertion
always_ff @ (posedge clk) begin always_ff @ (posedge clk) begin
AssertionExample: assert (!reset_l || count_c<100); AssertionExample: assert(!reset_l || count_c<100);
end end
// And example coverage analysis // And example coverage analysis

2
nodist/dot_importer
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@ -24,7 +24,7 @@ $Debug = 0;
my $opt_filename; my $opt_filename;
autoflush STDOUT 1; autoflush STDOUT 1;
autoflush STDERR 1; autoflush STDERR 1;
if (! GetOptions ( if (! GetOptions(
"help" => \&usage, "help" => \&usage,
"debug" => \&debug, "debug" => \&debug,
"<>" => \&parameter, "<>" => \&parameter,

2
nodist/dot_pruner
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@ -26,7 +26,7 @@ my $opt_filename;
my $opt_circle; my $opt_circle;
autoflush STDOUT 1; autoflush STDOUT 1;
autoflush STDERR 1; autoflush STDERR 1;
if (! GetOptions ( if (! GetOptions(
"help" => \&usage, "help" => \&usage,
"debug" => \&debug, "debug" => \&debug,
"<>" => \&parameter, "<>" => \&parameter,

2
nodist/install_test
View File

@ -18,7 +18,7 @@ our $Opt_Jobs = calc_jobs();
autoflush STDOUT 1; autoflush STDOUT 1;
autoflush STDERR 1; autoflush STDERR 1;
Getopt::Long::config("no_auto_abbrev"); Getopt::Long::config("no_auto_abbrev");
if (! GetOptions ( if (! GetOptions(
"debug" => sub { $Debug = 1; }, "debug" => sub { $Debug = 1; },
"<>" => sub { die "%Error: Unknown parameter: $_[0]\n"; }, "<>" => sub { die "%Error: Unknown parameter: $_[0]\n"; },
"stage=i" => \$Opt_Stage, "stage=i" => \$Opt_Stage,

2
nodist/vtree_importer
View File

@ -23,7 +23,7 @@ $Debug = 0;
my $opt_filename; my $opt_filename;
autoflush STDOUT 1; autoflush STDOUT 1;
autoflush STDERR 1; autoflush STDERR 1;
if (! GetOptions ( if (! GetOptions(
"help" => \&usage, "help" => \&usage,
"debug" => \&debug, "debug" => \&debug,
"<>" => \&parameter, "<>" => \&parameter,

16
src/astgen
View File

@ -7,7 +7,7 @@ use Getopt::Long;
use IO::File; use IO::File;
use Pod::Usage; use Pod::Usage;
use strict; use strict;
use vars qw ($Debug @Types %Classes %Children %ClassRefs %Stages); use vars qw($Debug @Types %Classes %Children %ClassRefs %Stages);
#====================================================================== #======================================================================
# main # main
@ -17,8 +17,8 @@ my $opt_classes;
my $opt_report; my $opt_report;
my @Opt_Cpt; my @Opt_Cpt;
my @Opt_I; my @Opt_I;
Getopt::Long::config ("pass_through", "no_auto_abbrev"); Getopt::Long::config("pass_through", "no_auto_abbrev");
if (! GetOptions ( if (! GetOptions(
"help" => \&usage, "help" => \&usage,
"debug" => sub { $Debug = 1; }, "debug" => sub { $Debug = 1; },
"classes!" => \$opt_classes, "classes!" => \$opt_classes,
@ -51,7 +51,7 @@ foreach my $cpt (@Opt_Cpt) {
sub usage { sub usage {
pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT); pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT);
exit (1); exit(1);
} }
sub parameter { sub parameter {
@ -355,7 +355,7 @@ sub process {
$self->{in_linenum} = $.; $self->{in_linenum} = $.;
$self->print("//$line"); $self->print("//$line");
$self->output_func(sub{my $self=shift; $self->_output_line(); }); $self->output_func(sub{my $self=shift; $self->_output_line(); });
$self->tree_line ($func); $self->tree_line($func);
$didln = 0; $didln = 0;
} }
elsif ($line !~ /^\s*\/[\/\*]\s*TREE/ elsif ($line !~ /^\s*\/[\/\*]\s*TREE/
@ -567,7 +567,7 @@ sub treeop_exec_func {
sub tree_match { sub tree_match {
my $self = shift; my $self = shift;
$self->print (" // TREEOP functions, each return true if they matched & transformed\n"); $self->print(" // TREEOP functions, each return true if they matched & transformed\n");
#use Data::Dumper; print Dumper($self); #use Data::Dumper; print Dumper($self);
foreach my $base (sort (keys %{$self->{treeop}})) { foreach my $base (sort (keys %{$self->{treeop}})) {
foreach my $typefunc (@{$self->{treeop}{$base}}) { foreach my $typefunc (@{$self->{treeop}{$base}}) {
@ -588,8 +588,8 @@ sub tree_match {
sub tree_base { sub tree_base {
my $self = shift; my $self = shift;
$self->print (" // TREEOP visitors, call each base type's match\n"); $self->print(" // TREEOP visitors, call each base type's match\n");
$self->print (" // Bottom class up, as more simple transforms are generally better\n"); $self->print(" // Bottom class up, as more simple transforms are generally better\n");
foreach my $type (sort (keys %::Classes)) { foreach my $type (sort (keys %::Classes)) {
my $base = $::Classes{$type}; my $base = $::Classes{$type};
my @out_for_type_sc; my @out_for_type_sc;

10
src/bisonpre
View File

@ -7,7 +7,7 @@ use Getopt::Long;
use IO::File; use IO::File;
use Pod::Usage; use Pod::Usage;
use strict; use strict;
use vars qw ($Debug $VERSION); use vars qw($Debug $VERSION);
$VERSION = '3.404'; $VERSION = '3.404';
@ -28,8 +28,8 @@ our $Opt_Input;
autoflush STDOUT 1; autoflush STDOUT 1;
autoflush STDERR 1; autoflush STDERR 1;
Getopt::Long::config ("no_auto_abbrev"); Getopt::Long::config("no_auto_abbrev");
if (! GetOptions ( if (! GetOptions(
# Local options # Local options
"help" => \&usage, "help" => \&usage,
"version" => sub { print "Version $VERSION\n"; exit(0); }, "version" => sub { print "Version $VERSION\n"; exit(0); },
@ -57,7 +57,7 @@ process();
sub usage { sub usage {
print "Version $VERSION\n"; print "Version $VERSION\n";
pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1); pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1);
exit (1); exit(1);
} }
sub parameter { sub parameter {
@ -328,7 +328,7 @@ sub clean_input {
($line =~ s/BISONPRE_NOT\((\S+)\)\s*(\{[^}]+})\s*$//) ($line =~ s/BISONPRE_NOT\((\S+)\)\s*(\{[^}]+})\s*$//)
or die "%Error: $filename:$l: Bad form of BISONPRE_NOT: $line\n"; or die "%Error: $filename:$l: Bad form of BISONPRE_NOT: $line\n";
my $endtok = $1; my $action = $2; my $endtok = $1; my $action = $2;
my @endtoks = split (/,/, $endtok); my @endtoks = split(/,/, $endtok);
map { $tokens{$_} or die "%Error: $filename:$l: Can't find definition for token: $_\n" map { $tokens{$_} or die "%Error: $filename:$l: Can't find definition for token: $_\n"
} @endtoks; } @endtoks;
# Push it all onto one line to avoid error messages changing # Push it all onto one line to avoid error messages changing

8
src/cppcheck_filtered
View File

@ -7,7 +7,7 @@ use Getopt::Long;
use IO::File; use IO::File;
use Pod::Usage; use Pod::Usage;
use strict; use strict;
use vars qw ($Debug $VERSION); use vars qw($Debug $VERSION);
$VERSION = '3.881'; $VERSION = '3.881';
@ -23,9 +23,9 @@ our $Opt_Debug;
autoflush STDOUT 1; autoflush STDOUT 1;
autoflush STDERR 1; autoflush STDERR 1;
Getopt::Long::config ("no_auto_abbrev","pass_through"); Getopt::Long::config("no_auto_abbrev","pass_through");
our @Opt_Args = ("cppcheck", @ARGV); our @Opt_Args = ("cppcheck", @ARGV);
if (! GetOptions ( if (! GetOptions(
# Local options # Local options
"help" => \&usage, "help" => \&usage,
"version" => sub { print "Version $VERSION\n"; system("cppcheck","--version"); exit(0); }, "version" => sub { print "Version $VERSION\n"; system("cppcheck","--version"); exit(0); },
@ -40,7 +40,7 @@ process();
sub usage { sub usage {
print "Version $VERSION\n"; print "Version $VERSION\n";
pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1); pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT, -noperldoc=>1);
exit (1); exit(1);
} }
####################################################################### #######################################################################

8
src/vlcovgen
View File

@ -7,7 +7,7 @@ use Getopt::Long;
use IO::File; use IO::File;
use Pod::Usage; use Pod::Usage;
use strict; use strict;
use vars qw ($Debug); use vars qw($Debug);
our @Items; our @Items;
@ -16,8 +16,8 @@ our @Items;
$Debug = 0; $Debug = 0;
my $Opt_Srcdir = "."; my $Opt_Srcdir = ".";
Getopt::Long::config ("pass_through", "no_auto_abbrev"); Getopt::Long::config("pass_through", "no_auto_abbrev");
if (! GetOptions ( if (! GetOptions(
"help" => \&usage, "help" => \&usage,
"debug" => sub { $Debug = 1; }, "debug" => sub { $Debug = 1; },
"srcdir=s" => \$Opt_Srcdir, "srcdir=s" => \$Opt_Srcdir,
@ -34,7 +34,7 @@ write_keys("$Opt_Srcdir/../include/verilated_cov_key.h");
sub usage { sub usage {
pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT); pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT);
exit (1); exit(1);
} }
####################################################################### #######################################################################

4
test_regress/driver.pl
View File

@ -21,7 +21,7 @@ use IO::File;
use Pod::Usage; use Pod::Usage;
use Data::Dumper; $Data::Dumper::Sortkeys=1; use Data::Dumper; $Data::Dumper::Sortkeys=1;
use strict; use strict;
use vars qw ($Debug %Vars $Driver $Fork); use vars qw($Debug %Vars $Driver $Fork);
use POSIX qw(strftime); use POSIX qw(strftime);
use lib "."; use lib ".";
@ -167,7 +167,7 @@ sub one_test {
test_pl_filename => $params{pl_filename}, test_pl_filename => $params{pl_filename},
run_on_start => sub { run_on_start => sub {
# Running in context of child, so can't pass data to parent directly # Running in context of child, so can't pass data to parent directly
print ("="x70,"\n"); print("="x70,"\n");
my $test = VTest->new(@params); my $test = VTest->new(@params);
$test->oprint("="x50,"\n"); $test->oprint("="x50,"\n");
unlink $test->{status_filename}; unlink $test->{status_filename};

3
test_regress/t/TestSimulator.h
View File

@ -34,7 +34,8 @@ public:
m_simulators.verilator = true; m_simulators.verilator = true;
} else if (0 == strcmp(m_info.product, "Verilator")) { } else if (0 == strcmp(m_info.product, "Verilator")) {
m_simulators.icarus = true; m_simulators.icarus = true;
} else if (0 == strncmp(m_info.product, "Chronologic Simulation VCS", strlen("Chronologic Simulation VCS"))) { } else if (0 == strncmp(m_info.product, "Chronologic Simulation VCS",
strlen("Chronologic Simulation VCS"))) {
m_simulators.vcs = true; m_simulators.vcs = true;
} else { } else {
printf("%%Warning: %s:%d: Unknown simulator in TestSimulator.h: %s\n", printf("%%Warning: %s:%d: Unknown simulator in TestSimulator.h: %s\n",

2
test_regress/t/TestVpi.h
View File

@ -24,7 +24,7 @@ class TestVpiHandle {
public: public:
TestVpiHandle() : m_handle(NULL), m_free(true) { } TestVpiHandle() : m_handle(NULL), m_free(true) { }
TestVpiHandle(vpiHandle h) : m_handle(h), m_free(true) { } TestVpiHandle(vpiHandle h) : m_handle(h), m_free(true) { }
~TestVpiHandle() { if (m_handle && m_free) { vpi_free_object(m_handle); m_handle=NULL; } } // icarus has yet to catch up with 1800-2009 ~TestVpiHandle() { if (m_handle && m_free) { vpi_free_object(m_handle); m_handle=NULL; } }
operator vpiHandle() const { return m_handle; } operator vpiHandle() const { return m_handle; }
inline TestVpiHandle& operator= (vpiHandle h) { m_handle = h; return *this; } inline TestVpiHandle& operator= (vpiHandle h) { m_handle = h; return *this; }
TestVpiHandle& nofree() { TestVpiHandle& nofree() {

2
test_regress/t/t_alw_split_rst.pl
View File

@ -14,7 +14,7 @@ compile(
); );
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
file_grep ($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0);
} }
execute( execute(

2
test_regress/t/t_alw_splitord.pl
View File

@ -14,7 +14,7 @@ compile(
); );
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
file_grep ($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0);
} }
execute( execute(

2
test_regress/t/t_assert_elab_bad.pl
View File

@ -23,7 +23,7 @@ execute(
fails => $Self->{vlt_all}, fails => $Self->{vlt_all},
); );
file_grep ("$Self->{obj_dir}/vlt_compile.log", file_grep("$Self->{obj_dir}/vlt_compile.log",
qr/%Warning-USERFATAL: Parameter 5 is invalid...string and constant both work/); qr/%Warning-USERFATAL: Parameter 5 is invalid...string and constant both work/);
ok(1); ok(1);

4
test_regress/t/t_assert_property_fail_1.pl
View File

@ -20,9 +20,9 @@ execute(
fails => 1 fails => 1
); );
file_grep ($Self->{run_log_filename}, qr/'assert property' failed/); file_grep($Self->{run_log_filename}, qr/'assert property' failed/);
# We expect to get a message when this assert fires: # We expect to get a message when this assert fires:
file_grep ($Self->{run_log_filename}, qr/cyc != 3/); file_grep($Self->{run_log_filename}, qr/cyc != 3/);
ok(1); ok(1);
1; 1;

2
test_regress/t/t_assert_property_fail_2.pl
View File

@ -20,7 +20,7 @@ execute(
fails => 1 fails => 1
); );
file_grep ($Self->{run_log_filename}, qr/'assert property' failed/); file_grep($Self->{run_log_filename}, qr/'assert property' failed/);
ok(1); ok(1);
1; 1;

6
test_regress/t/t_case_huge_prof.pl
View File

@ -15,8 +15,8 @@ compile(
verilator_flags2 => ["--stats --prof-cfuncs -CFLAGS '-pg' -LDFLAGS '-pg'"], verilator_flags2 => ["--stats --prof-cfuncs -CFLAGS '-pg' -LDFLAGS '-pg'"],
); );
file_grep ($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10); file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10);
file_grep ($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 10); file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 10);
unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*");
$ENV{GMON_OUT_PREFIX} = "$Self->{obj_dir}/gmon.out"; $ENV{GMON_OUT_PREFIX} = "$Self->{obj_dir}/gmon.out";
@ -36,7 +36,7 @@ run(cmd => ["cd $Self->{obj_dir} && gprof $Self->{VM_PREFIX} $gmon_base > gprof.
run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc gprof.out > cfuncs.out"], run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc gprof.out > cfuncs.out"],
check_finished => 0); check_finished => 0);
file_grep ("$Self->{obj_dir}/cfuncs.out", qr/Overall summary by/); file_grep("$Self->{obj_dir}/cfuncs.out", qr/Overall summary by/);
ok(1); ok(1);
1; 1;

2
test_regress/t/t_cdc_async_bad.pl
View File

@ -18,7 +18,7 @@ compile(
expect_filename => $Self->{golden_filename}, expect_filename => $Self->{golden_filename},
); );
file_grep ("$Self->{obj_dir}/V$Self->{name}__cdc.txt", qr/CDC Report/); file_grep("$Self->{obj_dir}/V$Self->{name}__cdc.txt", qr/CDC Report/);
ok(1); ok(1);
1; 1;

2
test_regress/t/t_cellarray.pl
View File

@ -18,7 +18,7 @@ execute(
); );
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
file_grep ($Self->{stats}, qr/Optimizations, Gate assign merged\s+(\d+)/i, 28); file_grep($Self->{stats}, qr/Optimizations, Gate assign merged\s+(\d+)/i, 28);
}; };
ok(1); ok(1);

2
test_regress/t/t_cover_toggle.pl
View File

@ -20,7 +20,7 @@ execute(
# Read the input .v file and do any CHECK_COVER requests # Read the input .v file and do any CHECK_COVER requests
inline_checks(); inline_checks();
file_grep ($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/i, 25) file_grep($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/i, 25)
if $Self->{vlt_all}; if $Self->{vlt_all};
ok(1); ok(1);

2
test_regress/t/t_dedupe_clk_gate.pl
View File

@ -14,7 +14,7 @@ compile(
); );
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
file_grep ($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 4); file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 4);
} }
ok(1); ok(1);

2
test_regress/t/t_dedupe_seq_logic.pl
View File

@ -14,7 +14,7 @@ compile(
); );
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
file_grep ($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 6); file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 6);
} }
ok(1); ok(1);

2
test_regress/t/t_display_merge.pl
View File

@ -18,7 +18,7 @@ execute(
expect_filename => $Self->{golden_filename}, expect_filename => $Self->{golden_filename},
); );
file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}__stats.txt", file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}__stats.txt",
qr/Node count, DISPLAY \s+ 32 \s+ 25 \s+ 25 \s+ 25/); qr/Node count, DISPLAY \s+ 32 \s+ 25 \s+ 25 \s+ 25/);
ok(1); ok(1);

528
test_regress/t/t_dpi_accessors.cpp
View File

@ -35,10 +35,10 @@ using std::setw;
// Convenience function to check we didn't finish unexpectedly // Convenience function to check we didn't finish unexpectedly
static void checkFinish(const char *msg) { static void checkFinish(const char *msg) {
if (Verilated::gotFinish ()) { if (Verilated::gotFinish ()) {
vl_fatal (__FILE__, __LINE__, "dut", msg); vl_fatal(__FILE__, __LINE__, "dut", msg);
exit (1); exit(1);
} }
} // checkFinish () }
// Convenience function to log the value of a register in hex. Only in verbose // Convenience function to log the value of a register in hex. Only in verbose
@ -50,12 +50,12 @@ static void logReg(int clk,
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
cout << "clk = " << clk << ", " << desc << " = " << val << note << endl; cout << "clk = " << clk << ", " << desc << " = " << val << note << endl;
#endif #endif
} // logReg () }
// Convenience function to log the value of a register in hex. Only in verbose // Convenience function to log the value of a register in hex. Only in verbose
// mode. // mode.
static void logRegHex (int clk, static void logRegHex(int clk,
const char *desc, const char *desc,
int bitWidth, int bitWidth,
int val, int val,
@ -63,61 +63,60 @@ static void logRegHex (int clk,
{ {
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
cout << "clk = " << clk << ", " << desc << " = " << bitWidth << "\'h" << hex cout << "clk = " << clk << ", " << desc << " = " << bitWidth << "\'h" << hex
<< setw ((bitWidth - 1) / 4 + 1) << setfill ('0') << val << setw((bitWidth - 1) / 4 + 1) << setfill('0') << val
<< setfill (' ') << setw (0) << dec << note << endl; << setfill(' ') << setw(0) << dec << note << endl;
#endif #endif
} // logRegHex () }
// Convenience function to check we got an expected result. Silent on success. // Convenience function to check we got an expected result. Silent on success.
static void checkResult (bool p, static void checkResult(bool p, const char *msg_fail) {
const char *msg_fail) {
if (!p) { if (!p) {
vl_fatal (__FILE__, __LINE__, "dut", msg_fail); vl_fatal(__FILE__, __LINE__, "dut", msg_fail);
} }
} // checkResult () }
// Main function instantiates the model and steps through the test. // Main function instantiates the model and steps through the test.
int main () { int main() {
Vt_dpi_accessors *dut = new Vt_dpi_accessors ("dut"); Vt_dpi_accessors *dut = new Vt_dpi_accessors ("dut");
svSetScope (svGetScopeFromName ("dut.t")); svSetScope(svGetScopeFromName("dut.t"));
// evaluate the model with no signal changes to get the initial blocks // evaluate the model with no signal changes to get the initial blocks
// executed. // executed.
dut->eval (); dut->eval();
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
cout << "Initial DPI values" << endl; cout << "Initial DPI values" << endl;
cout << "==================" << endl; cout << "==================" << endl;
#endif #endif
int a = (int) a_read (); int a = (int) a_read();
int b = (int) b_read (); int b = (int) b_read();
int mem32 = (int) mem32_read (); int mem32 = (int) mem32_read();
int c = (int) c_read (); int c = (int) c_read();
int d = (int) d_read (); int d = (int) d_read();
int e = (int) e_read (); int e = (int) e_read();
int f = (int) f_read (); int f = (int) f_read();
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
cout << "Read a = " << a << endl; cout << "Read a = " << a << endl;
cout << "Read b = 8'h" << hex << setw (2) << setfill ('0') << b cout << "Read b = 8'h" << hex << setw(2) << setfill('0') << b
<< setfill (' ') << setw (0) << dec << endl; << setfill(' ') << setw(0) << dec << endl;
cout << "Read mem32 = 8'h" << hex << setw (2) << setfill ('0') << mem32 cout << "Read mem32 = 8'h" << hex << setw(2) << setfill('0') << mem32
<< setfill (' ') << setw (0) << dec << endl; << setfill(' ') << setw(0) << dec << endl;
cout << "Read c = " << c << endl; cout << "Read c = " << c << endl;
cout << "Read d = 8'h" << hex << setw (2) << setfill ('0') << d cout << "Read d = 8'h" << hex << setw(2) << setfill('0') << d
<< setfill (' ') << setw (0) << dec << endl; << setfill(' ') << setw(0) << dec << endl;
cout << "Read e = 8'h" << hex << setw (2) << setfill ('0') << e cout << "Read e = 8'h" << hex << setw(2) << setfill('0') << e
<< setfill (' ') << setw (0) << dec << endl; << setfill(' ') << setw(0) << dec << endl;
cout << "Read f = 8'h" << hex << setw (2) << setfill ('0') << f cout << "Read f = 8'h" << hex << setw(2) << setfill('0') << f
<< setfill (' ') << setw (0) << dec << endl; << setfill(' ') << setw(0) << dec << endl;
cout << endl; cout << endl;
#endif #endif
checkResult ((0 == a) && (0x00 == b) && (0x20 == mem32) && (1 == c) checkResult((0 == a) && (0x00 == b) && (0x20 == mem32) && (1 == c)
&& (0xff == d) && (0x00 == e) && (0x00 == f), && (0xff == d) && (0x00 == e) && (0x00 == f),
"Bad initial DPI values."); "Bad initial DPI values.");
@ -132,23 +131,23 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
a = (int) a_read (); a = (int) a_read();
logReg (dut->clk, "read a", a, " (before clk)"); logReg(dut->clk, "read a", a, " (before clk)");
dut->eval (); dut->eval();
int a_after = (int) a_read (); int a_after = (int) a_read();
logReg (dut->clk, "read a", a_after, " (after clk)"); logReg(dut->clk, "read a", a_after, " (after clk)");
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
cout << endl; cout << endl;
#endif #endif
// On a posedge, a should toggle, on a negedge it should stay the // On a posedge, a should toggle, on a negedge it should stay the
// same. // same.
checkResult ( ((dut->clk == 1) && (a_after == (1 - a))) checkResult(((dut->clk == 1) && (a_after == (1 - a)))
|| ((dut->clk == 0) && (a_after == a )), || ((dut->clk == 0) && (a_after == a )),
"Test of scalar register reading failed."); "Test of scalar register reading failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can read a vector register. // Check we can read a vector register.
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -158,20 +157,20 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int) b_read (); b = (int) b_read();
logRegHex (dut->clk, "read b", 8, b, " (before clk)"); logRegHex(dut->clk, "read b", 8, b, " (before clk)");
dut->eval (); dut->eval();
int b_after = (int) b_read (); int b_after = (int) b_read();
logRegHex (dut->clk, "read b", 8, b_after, " (after clk)"); logRegHex(dut->clk, "read b", 8, b_after, " (after clk)");
// b should increment on a posedge and stay the same on a negedge. // b should increment on a posedge and stay the same on a negedge.
checkResult ( ((dut->clk == 1) && (b_after == (b + 1))) checkResult(((dut->clk == 1) && (b_after == (b + 1)))
|| ((dut->clk == 0) && (b_after == b )), || ((dut->clk == 0) && (b_after == b )),
"Test of vector register reading failed."); "Test of vector register reading failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Test we can read an array element // Test we can read an array element
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -182,20 +181,20 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
logRegHex (dut->clk, "read mem32", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)");
dut->eval (); dut->eval();
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
logRegHex (dut->clk, "read mem32", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)");
// In this case, the value never changes. But we should check it is // In this case, the value never changes. But we should check it is
// waht we expect (0x20). // waht we expect (0x20).
checkResult (mem32 == 0x20, "Test of array element reading failed."); checkResult(mem32 == 0x20, "Test of array element reading failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can read a scalar wire // Check we can read a scalar wire
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -206,25 +205,25 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
a = (int) a_read (); a = (int) a_read();
c = (int) c_read (); c = (int) c_read();
logReg (dut->clk, "read a", a, " (before clk)"); logReg(dut->clk, "read a", a, " (before clk)");
logReg (dut->clk, "read c", c, " (before clk)"); logReg(dut->clk, "read c", c, " (before clk)");
dut->eval (); dut->eval();
a = (int) a_read (); a = (int) a_read();
c = (int) c_read (); c = (int) c_read();
logReg (dut->clk, "read a", a, " (after clk)"); logReg(dut->clk, "read a", a, " (after clk)");
logReg (dut->clk, "read c", c, " (after clk)"); logReg(dut->clk, "read c", c, " (after clk)");
// "c" is continuously assigned as the inverse of "a", but in // "c" is continuously assigned as the inverse of "a", but in
// Verilator, that means that it will only change value when "a" // Verilator, that means that it will only change value when "a"
// changes on the posedge of a clock. Put simply, "c" always holds the // changes on the posedge of a clock. Put simply, "c" always holds the
// inverse of the "after clock" value of "a". // inverse of the "after clock" value of "a".
checkResult (c == (1 - a), "Test of scalar wire reading failed."); checkResult(c == (1 - a), "Test of scalar wire reading failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can read a vector wire // Check we can read a vector wire
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -235,26 +234,26 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int) b_read (); b = (int) b_read();
d = (int) d_read (); d = (int) d_read();
logRegHex (dut->clk, "read b", 8, b, " (before clk)"); logRegHex(dut->clk, "read b", 8, b, " (before clk)");
logRegHex (dut->clk, "read d", 8, d, " (before clk)"); logRegHex(dut->clk, "read d", 8, d, " (before clk)");
dut->eval (); dut->eval();
b = (int) b_read (); b = (int) b_read();
d = (int) d_read (); d = (int) d_read();
logRegHex (dut->clk, "read b", 8, b, " (after clk)"); logRegHex(dut->clk, "read b", 8, b, " (after clk)");
logRegHex (dut->clk, "read d", 8, d, " (after clk)"); logRegHex(dut->clk, "read d", 8, d, " (after clk)");
// "d" is continuously assigned as the (8-bit) bitwise inverse of "b", // "d" is continuously assigned as the (8-bit) bitwise inverse of "b",
// but in Verilator, that means that it will only change value when // but in Verilator, that means that it will only change value when
// "b" changes on the posedge of a clock. Put simply, "d" always holds // "b" changes on the posedge of a clock. Put simply, "d" always holds
// the inverse of the "after clock" value of "b". // the inverse of the "after clock" value of "b".
checkResult (d == ((~b) & 0xff), "Test of vector wire reading failed."); checkResult(d == ((~b) & 0xff), "Test of vector wire reading failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can write a scalar register // Check we can write a scalar register
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -265,25 +264,25 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
a = 1 - (int) a_read (); a = 1 - (int) a_read();
a_write (a); a_write(a);
logReg (dut->clk, "write a", a, " (before clk)"); logReg(dut->clk, "write a", a, " (before clk)");
a = a_read (); a = a_read();
logReg (dut->clk, "read a", a, " (before clk)"); logReg(dut->clk, "read a", a, " (before clk)");
dut->eval (); dut->eval();
int a_after = (int) a_read (); int a_after = (int) a_read();
logReg (dut->clk, "read a", a_after, " (after clk)"); logReg(dut->clk, "read a", a_after, " (after clk)");
// On a posedge clock, the value of a that is written should toggle, // On a posedge clock, the value of a that is written should toggle,
// on a negedge, it should not. // on a negedge, it should not.
checkResult ( ((dut->clk == 1) && (a_after == (1 - a))) checkResult(((dut->clk == 1) && (a_after == (1 - a)))
|| ((dut->clk == 0) && (a_after == a )), || ((dut->clk == 0) && (a_after == a )),
"Test of scalar register writing failed."); "Test of scalar register writing failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can write a vector register // Check we can write a vector register
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -294,25 +293,25 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int) b_read () - 1; b = (int) b_read() - 1;
b_write ((const svBitVecVal *) &b); b_write((const svBitVecVal *) &b);
logRegHex (dut->clk, "write b", 8, b, " (before clk)"); logRegHex(dut->clk, "write b", 8, b, " (before clk)");
b = (int) b_read (); b = (int) b_read();
logRegHex (dut->clk, "read b", 8, b, " (before clk)"); logRegHex(dut->clk, "read b", 8, b, " (before clk)");
dut->eval (); dut->eval();
int b_after = (int) b_read (); int b_after = (int) b_read();
logRegHex (dut->clk, "read b", 8, b_after, " (after clk)"); logRegHex(dut->clk, "read b", 8, b_after, " (after clk)");
// The value of "b" written should increment on a posedge and stay the // The value of "b" written should increment on a posedge and stay the
// same on a negedge. // same on a negedge.
checkResult ( ((dut->clk == 1) && (b_after == (b + 1))) checkResult(((dut->clk == 1) && (b_after == (b + 1)))
|| ((dut->clk == 0) && (b_after == b )), || ((dut->clk == 0) && (b_after == b )),
"Test of vector register writing failed."); "Test of vector register writing failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Test we can write an array element // Test we can write an array element
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -323,26 +322,26 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
mem32 = (int) mem32_read () - 1; mem32 = (int) mem32_read() - 1;
mem32_write ((const svBitVecVal *) &mem32); mem32_write((const svBitVecVal *) &mem32);
logRegHex (dut->clk, "write mem32", 8, mem32, " (before clk)"); logRegHex(dut->clk, "write mem32", 8, mem32, " (before clk)");
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
logRegHex (dut->clk, "read mem32", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)");
dut->eval (); dut->eval();
int mem32_after = (int) mem32_read (); int mem32_after = (int) mem32_read();
logRegHex (dut->clk, "read mem32", 8, mem32_after, " (after clk)"); logRegHex(dut->clk, "read mem32", 8, mem32_after, " (after clk)");
// In this case, the value we write never changes (this would only // In this case, the value we write never changes (this would only
// happen if this part of the test coincided with the 32nd element // happen if this part of the test coincided with the 32nd element
// being overwritten, which it does not. Check that the value after // being overwritten, which it does not. Check that the value after
// the clock is the same as before the clock. // the clock is the same as before the clock.
checkResult (mem32_after == mem32, checkResult(mem32_after == mem32,
"Test of array element writing failed."); "Test of array element writing failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can read a vector register slice // Check we can read a vector register slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -353,24 +352,24 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int) b_read (); b = (int) b_read();
int b_slice = (int) b_slice_read (); int b_slice = (int) b_slice_read();
logRegHex (dut->clk, "read b [7:0]", 8, b, " (before clk)"); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before clk)");
logRegHex (dut->clk, "read b [3:0]", 4, b_slice, " (before clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (before clk)");
dut->eval (); dut->eval();
b = (int) b_read (); b = (int) b_read();
b_slice = (int) b_slice_read (); b_slice = (int) b_slice_read();
logRegHex (dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)");
logRegHex (dut->clk, "read b [3:0]", 4, b_slice, " (after clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)");
// The slice of "b" should always be the bottom 4 bits of "b" // The slice of "b" should always be the bottom 4 bits of "b"
checkResult (b_slice == (b & 0x0f), checkResult(b_slice == (b & 0x0f),
"Test of vector register slice reading failed."); "Test of vector register slice reading failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Test we can read an array element slice // Test we can read an array element slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -381,27 +380,27 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
int mem32_slice = (int) mem32_slice_read (); int mem32_slice = (int) mem32_slice_read();
logRegHex (dut->clk, "read mem32 [7:0] ", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (before clk)");
logRegHex (dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice,
" (before clk)"); " (before clk)");
dut->eval (); dut->eval();
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
mem32_slice = (int) mem32_slice_read (); mem32_slice = (int) mem32_slice_read();
logRegHex (dut->clk, "read mem32 [7:0] ", 8, mem32," (after clk)"); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32," (after clk)");
logRegHex (dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice,
" (after clk)"); " (after clk)");
// The slice of "mem32" should always be the concatenation of the top // The slice of "mem32" should always be the concatenation of the top
// 2 and bottom 3 bits of "mem32" // 2 and bottom 3 bits of "mem32"
checkResult (mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)), checkResult(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)),
"Test of array element slice reading failed."); "Test of array element slice reading failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can read a vector wire slice // Check we can read a vector wire slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -412,28 +411,28 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int) b_read (); b = (int) b_read();
d = (int) d_read (); d = (int) d_read();
int d_slice = (int) d_slice_read (); int d_slice = (int) d_slice_read();
logRegHex (dut->clk, "read b [7:0]", 8, b, " (before clk)"); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before clk)");
logRegHex (dut->clk, "read d [7:0]", 8, d, " (before clk)"); logRegHex(dut->clk, "read d [7:0]", 8, d, " (before clk)");
logRegHex (dut->clk, "read d [6:1]", 6, d_slice, " (before clk)"); logRegHex(dut->clk, "read d [6:1]", 6, d_slice, " (before clk)");
dut->eval (); dut->eval();
b = (int) b_read (); b = (int) b_read();
d = (int) d_read (); d = (int) d_read();
d_slice = (int) d_slice_read (); d_slice = (int) d_slice_read();
logRegHex (dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)");
logRegHex (dut->clk, "read d [7:0]", 8, d, " (after clk)"); logRegHex(dut->clk, "read d [7:0]", 8, d, " (after clk)");
logRegHex (dut->clk, "read d [6:1]", 6, d_slice, " (after clk)"); logRegHex(dut->clk, "read d [6:1]", 6, d_slice, " (after clk)");
// The slice of "d" should always be the middle 6 bits of "d". // The slice of "d" should always be the middle 6 bits of "d".
checkResult (d_slice == ((d & 0x7e) >> 1), checkResult(d_slice == ((d & 0x7e) >> 1),
"Test of vector wire slice reading failed."); "Test of vector wire slice reading failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can write a vector register slice // Check we can write a vector register slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -445,37 +444,37 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int) b_read (); b = (int) b_read();
int b_slice = (int) b_slice_read (); int b_slice = (int) b_slice_read();
logRegHex (dut->clk, "read b [7:0]", 8, b, " (before write)"); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before write)");
logRegHex (dut->clk, "read b [3:0]", 4, b_slice, " (before write)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (before write)");
b_slice--; b_slice--;
b_slice_write ((const svBitVecVal *) &b_slice); b_slice_write((const svBitVecVal *) &b_slice);
logRegHex (dut->clk, "write b [3:0]", 4, b_slice, " (before clk)"); logRegHex(dut->clk, "write b [3:0]", 4, b_slice, " (before clk)");
int b_after = (int) b_read (); int b_after = (int) b_read();
int b_slice_after = (int) b_slice_read (); int b_slice_after = (int) b_slice_read();
logRegHex (dut->clk, "read b [7:0]", 8, b_after, logRegHex(dut->clk, "read b [7:0]", 8, b_after,
" (before clk)"); " (before clk)");
logRegHex (dut->clk, "read b [3:0]", 4, b_slice_after, logRegHex(dut->clk, "read b [3:0]", 4, b_slice_after,
" (before clk)"); " (before clk)");
// We must test that when we wrote the slice of "b", we only wrote the // We must test that when we wrote the slice of "b", we only wrote the
// correct bits. The slice of b is b[3:0] // correct bits. The slice of b is b[3:0]
int b_new = (b & 0xf0) | (b_slice &0x0f); int b_new = (b & 0xf0) | (b_slice &0x0f);
checkResult (b_after == b_new, checkResult(b_after == b_new,
"Test of vector register slice writing failed."); "Test of vector register slice writing failed.");
dut->eval (); dut->eval();
b = (int) b_read (); b = (int) b_read();
b_slice = (int) b_slice_read (); b_slice = (int) b_slice_read();
logRegHex (dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)");
logRegHex (dut->clk, "read b [3:0]", 4, b_slice, " (after clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Test we can write an array element slice // Test we can write an array element slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -487,23 +486,23 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
int mem32_slice = (int) mem32_slice_read (); int mem32_slice = (int) mem32_slice_read();
logRegHex (dut->clk, "read mem32 [7:0] ", 8, mem32, logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32,
" (before write)"); " (before write)");
logRegHex (dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice,
" (before write)"); " (before write)");
mem32_slice--; mem32_slice--;
mem32_slice_write ((const svBitVecVal *) &mem32_slice); mem32_slice_write((const svBitVecVal *) &mem32_slice);
logRegHex (dut->clk, "write mem32 [7:6,2:0]", 5, mem32_slice, logRegHex(dut->clk, "write mem32 [7:6,2:0]", 5, mem32_slice,
" (before clk)"); " (before clk)");
int mem32_after = (int) mem32_read (); int mem32_after = (int) mem32_read();
int mem32_slice_after = (int) mem32_slice_read (); int mem32_slice_after = (int) mem32_slice_read();
logRegHex (dut->clk, "read mem32 [7:0] ", 8, mem32_after, logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32_after,
" (before clk)"); " (before clk)");
logRegHex (dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice_after, logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice_after,
" (before clk)"); " (before clk)");
// We must test that when we wrote the slice of "mem32", we only wrote // We must test that when we wrote the slice of "mem32", we only wrote
@ -511,25 +510,25 @@ int main () {
int mem32_new = (mem32 & 0x38) int mem32_new = (mem32 & 0x38)
| ((mem32_slice & 0x18) << 3) | | ((mem32_slice & 0x18) << 3) |
(mem32_slice & 0x7); (mem32_slice & 0x7);
checkResult (mem32_after == mem32_new, checkResult(mem32_after == mem32_new,
"Test of vector register slice writing failed."); "Test of vector register slice writing failed.");
dut->eval (); dut->eval();
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
mem32_slice = (int) mem32_slice_read (); mem32_slice = (int) mem32_slice_read();
logRegHex (dut->clk, "read mem32 [7:0] ", 8, mem32," (after clk)"); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32," (after clk)");
logRegHex (dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice,
" (after clk)"); " (after clk)");
// We have already tested that array element writing works, so we just // We have already tested that array element writing works, so we just
// check that dhe slice of "mem32" after the clock is the // check that dhe slice of "mem32" after the clock is the
// concatenation of the top 2 and bottom 3 bits of "mem32" // concatenation of the top 2 and bottom 3 bits of "mem32"
checkResult (mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)), checkResult(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)),
"Test of array element slice writing failed."); "Test of array element slice writing failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Check we can read complex registers // Check we can read complex registers
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -541,31 +540,31 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int) b_read (); b = (int) b_read();
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
e = (int) e_read (); e = (int) e_read();
int l1 = (int) l1_read (); int l1 = (int) l1_read();
logRegHex (dut->clk, "read b ", 8, b, " (before clk)"); logRegHex(dut->clk, "read b ", 8, b, " (before clk)");
logRegHex (dut->clk, "read mem32", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)");
logRegHex (dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e, " (before clk)");
logRegHex (dut->clk, "read l1 ", 15, l1, " (before clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (before clk)");
dut->eval (); dut->eval();
b = (int) b_read (); b = (int) b_read();
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
e = (int) e_read (); e = (int) e_read();
l1 = (int) l1_read (); l1 = (int) l1_read();
logRegHex (dut->clk, "read b ", 8, b, " (after clk)"); logRegHex(dut->clk, "read b ", 8, b, " (after clk)");
logRegHex (dut->clk, "read mem32", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)");
logRegHex (dut->clk, "read e ", 8, e, " (after clk)"); logRegHex(dut->clk, "read e ", 8, e, " (after clk)");
logRegHex (dut->clk, "read l1 ", 15, l1, " (after clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (after clk)");
// We have already tested that reading of registers, memory elements // We have already tested that reading of registers, memory elements
// and wires works. So we just need to check that l1 reads back as the // and wires works. So we just need to check that l1 reads back as the
// correct combination of bits after the clock. It should be the 15 // correct combination of bits after the clock. It should be the 15
// bits: {b[3:0],mem[32][7:6],e[6:1],mem[32][2:0]}. // bits: {b[3:0],mem[32][7:6],e[6:1],mem[32][2:0]}.
checkResult (l1 == ( (((b & 0x0f) >> 0) << 11) checkResult(l1 == ( (((b & 0x0f) >> 0) << 11)
| (((mem32 & 0xc0) >> 6) << 9) | (((mem32 & 0xc0) >> 6) << 9)
| (((e & 0x7e) >> 1) << 3) | (((e & 0x7e) >> 1) << 3)
| (((mem32 & 0x07) >> 0) << 0)), | (((mem32 & 0x07) >> 0) << 0)),
@ -576,41 +575,41 @@ int main () {
cout << endl; cout << endl;
#endif #endif
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
e = 0x05 | (i << 4); e = 0x05 | (i << 4);
f = 0xa0 | i; f = 0xa0 | i;
e_write ((const svBitVecVal *) &e); e_write((const svBitVecVal *) &e);
f_write ((const svBitVecVal *) &f); f_write((const svBitVecVal *) &f);
e = (int) e_read (); e = (int) e_read();
f = (int) f_read (); f = (int) f_read();
int l2 = (int) l2_read (); int l2 = (int) l2_read();
logRegHex (dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e, " (before clk)");
logRegHex (dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)");
logRegHex (dut->clk, "read l2", 8, l2, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)");
dut->eval (); dut->eval();
e = (int) e_read (); e = (int) e_read();
f = (int) f_read (); f = (int) f_read();
l2 = (int) l2_read (); l2 = (int) l2_read();
logRegHex (dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e, " (before clk)");
logRegHex (dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)");
logRegHex (dut->clk, "read l2", 8, l2, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)");
// We have already tested that reading of registers, memory elements // We have already tested that reading of registers, memory elements
// and wires works. So we just need to check that l1 reads back as the // and wires works. So we just need to check that l1 reads back as the
// correct combination of bits after the clock. It should be the 8 // correct combination of bits after the clock. It should be the 8
// bits: {e[7:4], f[3:0]}. // bits: {e[7:4], f[3:0]}.
checkResult (l2 == ((e & 0xf0) | (f & 0x0f)), checkResult(l2 == ((e & 0xf0) | (f & 0x0f)),
"Test of complex register reading l2 failed."); "Test of complex register reading l2 failed.");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Test we can write a complex register // Test we can write a complex register
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -622,25 +621,25 @@ int main () {
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int) b_read (); b = (int) b_read();
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
e = (int) e_read (); e = (int) e_read();
logRegHex (dut->clk, "read b ", 8, b, " (before write)"); logRegHex(dut->clk, "read b ", 8, b, " (before write)");
logRegHex (dut->clk, "read mem32", 8, mem32, " (before write)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before write)");
logRegHex (dut->clk, "read e ", 8, e, " (before write)"); logRegHex(dut->clk, "read e ", 8, e, " (before write)");
int l1 = 0x5a5a; int l1 = 0x5a5a;
l1_write ((const svBitVecVal *) &l1); l1_write((const svBitVecVal *) &l1);
logRegHex (dut->clk, "write l1 ", 15, l1, " (before clk)"); logRegHex(dut->clk, "write l1 ", 15, l1, " (before clk)");
int b_after = (int) b_read (); int b_after = (int) b_read();
int mem32_after = (int) mem32_read (); int mem32_after = (int) mem32_read();
int e_after = (int) e_read (); int e_after = (int) e_read();
int l1_after = (int) l1_read (); int l1_after = (int) l1_read();
logRegHex (dut->clk, "read b ", 8, b_after, " (before clk)"); logRegHex(dut->clk, "read b ", 8, b_after, " (before clk)");
logRegHex (dut->clk, "read mem32", 8, mem32_after, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32_after, " (before clk)");
logRegHex (dut->clk, "read e ", 8, e_after, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e_after, " (before clk)");
logRegHex (dut->clk, "read l1 ", 15, l1_after, " (before clk)"); logRegHex(dut->clk, "read l1 ", 15, l1_after, " (before clk)");
// We need to check that when we write l1, the correct fields, and // We need to check that when we write l1, the correct fields, and
// only the correct fields are set in its component registers, wires // only the correct fields are set in its component registers, wires
@ -649,73 +648,72 @@ int main () {
int b_new = (b & 0xf0) | ((l1 & 0x7800) >> 11); int b_new = (b & 0xf0) | ((l1 & 0x7800) >> 11);
int mem32_new = (mem32 & 0x38) | ((l1 & 0x0600) >> 3) | (l1 & 0x0007); int mem32_new = (mem32 & 0x38) | ((l1 & 0x0600) >> 3) | (l1 & 0x0007);
int e_new = (e & 0x81) | ((l1 & 0x01f8) >> 2); int e_new = (e & 0x81) | ((l1 & 0x01f8) >> 2);
checkResult ( (b_new == b_after) checkResult((b_new == b_after)
&& (mem32_new == mem32_after) && (mem32_new == mem32_after)
&& (e_new == e_after), && (e_new == e_after),
"Test of complex register writing l1 failed."); "Test of complex register writing l1 failed.");
dut->eval (); dut->eval();
b = (int) b_read (); b = (int) b_read();
mem32 = (int) mem32_read (); mem32 = (int) mem32_read();
d = (int) d_read (); d = (int) d_read();
l1 = (int) l1_read (); l1 = (int) l1_read();
logRegHex (dut->clk, "read b ", 8, b, " (after clk)"); logRegHex(dut->clk, "read b ", 8, b, " (after clk)");
logRegHex (dut->clk, "read mem32", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)");
logRegHex (dut->clk, "read d ", 8, d, " (after clk)"); logRegHex(dut->clk, "read d ", 8, d, " (after clk)");
logRegHex (dut->clk, "read l1 ", 15, l1, " (after clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (after clk)");
} }
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
cout << endl; cout << endl;
#endif #endif
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) { for (int i = 0; !Verilated::gotFinish () && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
e = (int) e_read (); e = (int) e_read();
f = (int) f_read (); f = (int) f_read();
logRegHex (dut->clk, "read e ", 8, e, " (before write)"); logRegHex(dut->clk, "read e ", 8, e, " (before write)");
logRegHex (dut->clk, "read f ", 8, f, " (before write)"); logRegHex(dut->clk, "read f ", 8, f, " (before write)");
int l2 = 0xa5 + i; int l2 = 0xa5 + i;
l2_write ((const svBitVecVal *) &l2); l2_write((const svBitVecVal *) &l2);
logRegHex (dut->clk, "write l2", 8, l2, " (before clk)"); logRegHex(dut->clk, "write l2", 8, l2, " (before clk)");
int e_after = (int) e_read (); int e_after = (int) e_read();
int f_after = (int) f_read (); int f_after = (int) f_read();
int l2_after = (int) l2_read (); int l2_after = (int) l2_read();
logRegHex (dut->clk, "read e ", 8, e_after, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e_after, " (before clk)");
logRegHex (dut->clk, "read f ", 8, f_after, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f_after, " (before clk)");
logRegHex (dut->clk, "read l2", 8, l2_after, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2_after, " (before clk)");
// We need to check that when we write l2, the correct fields, and // We need to check that when we write l2, the correct fields, and
// only the correct fields are set in its component registers. l is 8 // only the correct fields are set in its component registers. l is 8
// bits: {e[5:2], f[5:2]} // bits: {e[5:2], f[5:2]}
int e_new = (e & 0xc3) | ((l2 & 0xf0) >> 2); int e_new = (e & 0xc3) | ((l2 & 0xf0) >> 2);
int f_new = (f & 0xc3) | ((l2 & 0x0f) << 2); int f_new = (f & 0xc3) | ((l2 & 0x0f) << 2);
checkResult ((e_new == e_after) && (f_new == f_after), checkResult((e_new == e_after) && (f_new == f_after),
"Test of complex register writing l2 failed."); "Test of complex register writing l2 failed.");
dut->eval (); dut->eval();
e = (int) e_read (); e = (int) e_read();
f = (int) f_read (); f = (int) f_read();
l2 = (int) l2_read (); l2 = (int) l2_read();
logRegHex (dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e, " (before clk)");
logRegHex (dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)");
logRegHex (dut->clk, "read l2", 8, l2, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)");
} }
checkFinish ("t_dpi_accessors unexpected finish"); checkFinish("t_dpi_accessors unexpected finish");
// Tidy up // Tidy up
dut->final (); dut->final();
cout << "*-* All Finished *-*" << endl;; cout << "*-* All Finished *-*" << endl;;
}
} // main ()
// Local Variables: // Local Variables:
// c-file-style:"cc-mode" // c-file-style:"cc-mode"

24
test_regress/t/t_dpi_export_c.cpp
View File

@ -119,35 +119,35 @@ int dpix_run_tests() {
#ifndef CADENCE // Unimplemented; how hard is it? #ifndef CADENCE // Unimplemented; how hard is it?
printf("svDpiVersion: %s\n",svDpiVersion()); printf("svDpiVersion: %s\n",svDpiVersion());
CHECK_RESULT (bool, CHECK_RESULT(bool,
strcmp(svDpiVersion(), "1800-2005")==0 strcmp(svDpiVersion(), "1800-2005")==0
|| strcmp(svDpiVersion(), "P1800-2005")==0 || strcmp(svDpiVersion(), "P1800-2005")==0
, 1); , 1);
#endif #endif
CHECK_RESULT (int, dpix_int123(), 0x123 ); CHECK_RESULT(int, dpix_int123(), 0x123 );
#ifndef CADENCE // No export calls from an import #ifndef CADENCE // No export calls from an import
int o; int o;
dpix_t_int(0x456, &o); dpix_t_int(0x456, &o);
CHECK_RESULT (unsigned long, o, ~0x456UL); CHECK_RESULT(unsigned long, o, ~0x456UL);
dpix_t_renamed(0x456, &o); dpix_t_renamed(0x456, &o);
CHECK_RESULT (int, o, 0x458UL); CHECK_RESULT(int, o, 0x458UL);
#endif #endif
svBitVecVal vec10[1] = {0x10}; svBitVecVal vec10[1] = {0x10};
CHECK_RESULT (int, dpix_f_bit(1), 0x0); CHECK_RESULT(int, dpix_f_bit(1), 0x0);
CHECK_RESULT (int, dpix_f_bit(0), 0x1); CHECK_RESULT(int, dpix_f_bit(0), 0x1);
CHECK_RESULT (int, dpix_f_bit15(vec10) & 0x7fUL, 0x6f); CHECK_RESULT(int, dpix_f_bit15(vec10) & 0x7fUL, 0x6f);
// Simulators disagree over the next three's sign extension unless we mask the upper bits // Simulators disagree over the next three's sign extension unless we mask the upper bits
CHECK_RESULT (int, dpix_f_int(1) & 0xffffffffUL, 0xfffffffeUL); CHECK_RESULT(int, dpix_f_int(1) & 0xffffffffUL, 0xfffffffeUL);
CHECK_RESULT (int, dpix_f_byte(1) & 0xffUL, 0xfe); CHECK_RESULT(int, dpix_f_byte(1) & 0xffUL, 0xfe);
CHECK_RESULT (int, dpix_f_shortint(1) & 0xffffUL, 0xfffeUL); CHECK_RESULT(int, dpix_f_shortint(1) & 0xffffUL, 0xfffeUL);
CHECK_RESULT (unsigned long long, dpix_f_longint(1), 0xfffffffffffffffeULL); CHECK_RESULT(unsigned long long, dpix_f_longint(1), 0xfffffffffffffffeULL);
CHECK_RESULT (void*, dpix_f_chandle((void*)(12345)), (void*)(12345)); CHECK_RESULT(void*, dpix_f_chandle((void*)(12345)), (void*)(12345));
{ {
svBitVecVal i_vec48[2] = {0xab782a12,0x8a413bd9}; svBitVecVal i_vec48[2] = {0xab782a12,0x8a413bd9};

6
test_regress/t/t_dpi_import_c.cpp
View File

@ -149,12 +149,12 @@ void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o) {
o[1].bval = 0; o[1].bval = 0;
} }
void dpii_v_struct (const svBitVecVal* i, svBitVecVal* o) { void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o) {
o[0] = ~i[0]; o[0] = ~i[0];
o[1] = ~i[1]; o[1] = ~i[1];
o[2] = ~i[2]; o[2] = ~i[2];
} }
void dpii_v_substruct (const svBitVecVal* i, int* o) { void dpii_v_substruct(const svBitVecVal* i, int* o) {
// To be most like other tools, this should automagically take the substruct_t // To be most like other tools, this should automagically take the substruct_t
// as an argument, and not require this cast... // as an argument, and not require this cast...
substruct_t* issp = (substruct_t*) i; substruct_t* issp = (substruct_t*) i;
@ -175,7 +175,7 @@ void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o) {
o[2] = ~i[2]; o[2] = ~i[2];
} }
int dpii_f_strlen (const char* i) { return strlen(i); } int dpii_f_strlen(const char* i) { return strlen(i); }
//====================================================================== //======================================================================

2
test_regress/t/t_flag_skipidentical.pl
View File

@ -17,7 +17,7 @@ scenarios(vlt => 1);
print "Old mtime=",$oldstats[9],"\n"; print "Old mtime=",$oldstats[9],"\n";
$oldstats[9] or error("No output file found: $outfile\n"); $oldstats[9] or error("No output file found: $outfile\n");
sleep (1); # Or else it might take < 1 second to compile and see no diff. sleep(1); # Or else it might take < 1 second to compile and see no diff.
compile(); compile();

2
test_regress/t/t_gate_chained.pl
View File

@ -53,7 +53,7 @@ execute(
); );
# Must be <<9000 above to prove this worked # Must be <<9000 above to prove this worked
file_grep ($Self->{stats}, qr/Optimizations, Gate sigs deleted\s+(\d+)/i, 8575); file_grep($Self->{stats}, qr/Optimizations, Gate sigs deleted\s+(\d+)/i, 8575);
ok(1); ok(1);
1; 1;

2
test_regress/t/t_help.pl
View File

@ -22,7 +22,7 @@ foreach my $prog (
logfile => "$Self->{obj_dir}/t_help.log", logfile => "$Self->{obj_dir}/t_help.log",
tee => 0, tee => 0,
); );
file_grep ("$Self->{obj_dir}/t_help.log", qr/DISTRIBUTION/i); file_grep("$Self->{obj_dir}/t_help.log", qr/DISTRIBUTION/i);
} }
ok(1); ok(1);

2
test_regress/t/t_inst_tree_inl0_pub1.pl
View File

@ -38,7 +38,7 @@ sub checkRelativeRefs {
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
# We expect to combine sequent functions across multiple instances of # We expect to combine sequent functions across multiple instances of
# l2, l3, l4, l5. If this number drops, please confirm this has not broken. # l2, l3, l4, l5. If this number drops, please confirm this has not broken.
file_grep ($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i,
($Self->{vltmt} ? 84 : 52)); ($Self->{vltmt} ? 84 : 52));
# Expect absolute refs in CFuncs for t (top module) and l1 (because it # Expect absolute refs in CFuncs for t (top module) and l1 (because it

2
test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl
View File

@ -18,7 +18,7 @@ compile(
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
# Fewer optimizations than t_inst_tree_inl0_pub1 which allows # Fewer optimizations than t_inst_tree_inl0_pub1 which allows
# relative CFuncs: # relative CFuncs:
file_grep ($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i,
($Self->{vltmt} ? 0 : 31)); ($Self->{vltmt} ? 0 : 31));
# Should not find any 'this->' except some 'this->__VlSymsp' # Should not find any 'this->' except some 'this->__VlSymsp'

2
test_regress/t/t_mem_shift.pl
View File

@ -14,7 +14,7 @@ compile(
); );
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
file_grep ($Self->{stats}, qr/Optimizations, Delayed shared-sets\s+(\d+)/i, 14); file_grep($Self->{stats}, qr/Optimizations, Delayed shared-sets\s+(\d+)/i, 14);
} }
execute( execute(

4
test_regress/t/t_reloop_cam.pl
View File

@ -19,9 +19,9 @@ execute(
); );
if ($Self->{vlt_all}) { if ($Self->{vlt_all}) {
file_grep ($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/i, file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/i,
768); 768);
file_grep ($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/i, file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/i,
3); 3);
} }

2
test_regress/t/t_trace_array.pl
View File

@ -17,7 +17,7 @@ execute(
check_finished => 1, check_finished => 1,
); );
file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
ok(1); ok(1);
1; 1;

6
test_regress/t/t_vpi_memory.cpp
View File

@ -121,7 +121,7 @@ int _mon_check_range(TestVpiHandle& handle, int size, int left, int right) {
int _mon_check_memory() { int _mon_check_memory() {
int cnt; int cnt;
TestVpiHandle mem_h, lcl_h; TestVpiHandle mem_h, lcl_h;
vpiHandle iter_h; // icarus does not like auto free of iterator handles vpiHandle iter_h; // Icarus does not like auto free of iterator handles
s_vpi_value value = { s_vpi_value value = {
vpiIntVal, .value = {.integer = 0} vpiIntVal, .value = {.integer = 0}
}; };
@ -220,7 +220,8 @@ int main(int argc, char **argv, char **env) {
double sim_time = 1100; double sim_time = 1100;
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
Verilated::debug(0); Verilated::debug(0);
Verilated::fatalOnVpiError(0); // we're going to be checking for these errors do don't crash out // we're going to be checking for these errors do don't crash out
Verilated::fatalOnVpiError(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out
@ -266,4 +267,3 @@ int main(int argc, char **argv, char **env) {
} }
#endif #endif

3
test_regress/t/t_vpi_unimpl.cpp
View File

@ -151,7 +151,8 @@ int main(int argc, char **argv, char **env) {
double sim_time = 1100; double sim_time = 1100;
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
Verilated::debug(0); Verilated::debug(0);
Verilated::fatalOnVpiError(0); // we're going to be checking for these errors do don't crash out // we're going to be checking for these errors do don't crash out
Verilated::fatalOnVpiError(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out

31
test_regress/vgen.pl
View File

@ -9,13 +9,13 @@ use Pod::Usage;
use Data::Dumper; $Data::Dumper::Indent = 1; use Data::Dumper; $Data::Dumper::Indent = 1;
use Bit::Vector; use Bit::Vector;
use strict; use strict;
use vars qw ($Debug); use vars qw($Debug);
our @Orig_ARGV = @ARGV; our @Orig_ARGV = @ARGV;
our $Rerun_Args = $0." ".join(' ',@Orig_ARGV); our $Rerun_Args = $0." ".join(' ',@Orig_ARGV);
$Rerun_Args =~ s/\s+$//; $Rerun_Args =~ s/\s+$//;
use vars qw (@Blocks use vars qw(@Blocks
%Vars %Vars
%VarAttrs %VarAttrs
%VarsBlock %VarsBlock
@ -238,7 +238,7 @@ write_output_v($Opt_Output);
sub usage { sub usage {
pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT); pod2usage(-verbose=>2, -exitval=>2, -output=>\*STDOUT);
exit (1); exit(1);
} }
sub debug { sub debug {
@ -376,7 +376,7 @@ sub rnd_const {
} }
} elsif ($v<60) { # one } elsif ($v<60) { # one
$val->Word_Store(0,1); $val->Word_Store(0,1);
} else { #random } else { # random
for (my $w=0; $w<$val->Word_Size; ++$w) { for (my $w=0; $w<$val->Word_Size; ++$w) {
$val->Word_Store($w,rnd_int()); $val->Word_Store($w,rnd_int());
} }
@ -403,7 +403,7 @@ sub rnd {
} }
sub rnd32 { sub rnd32 {
my $vp = int(rand(1<<16)); my $vp = int(rand(1<<16));
$vp ^= (int(rand(1<<8)))<<16;# Single 1<<16 doesn't work $vp ^= (int(rand(1<<8)))<<16; # Single 1<<16 doesn't work
$vp ^= (int(rand(1<<8)))<<24; $vp ^= (int(rand(1<<8)))<<24;
return ($vp); return ($vp);
} }
@ -636,8 +636,8 @@ sub gen_leaf {
print " Value ",$treeref->{val}," = ",$treeref->val_to_text(),"\n" if $Debug; print " Value ",$treeref->{val}," = ",$treeref->val_to_text(),"\n" if $Debug;
#$treeref->tree_dump() if $Debug; #$treeref->tree_dump() if $Debug;
$treeref->{val_size} = $treeref->{val}->Size; #Debugging $treeref->{val_size} = $treeref->{val}->Size; # Debugging
$treeref->{val_text} = $treeref->{val}->to_Hex; #Debugging $treeref->{val_text} = $treeref->{val}->to_Hex; # Debugging
($treeref->{val}->Size == $treeref->{width}) ($treeref->{val}->Size == $treeref->{width})
or die "%Error: Size mismatch ",$treeref->{val}->Size,"!=",$treeref->{width},"\n",Dumper($treeref); or die "%Error: Size mismatch ",$treeref->{val}->Size,"!=",$treeref->{width},"\n",Dumper($treeref);
@ -749,7 +749,7 @@ sub decl_text {
my $decl_with = shift; my $decl_with = shift;
my $varref = $Vars{$var}; my $varref = $Vars{$var};
return sprintf (" reg %s [%3d:%3d] %s %s; //=%d'h%s" return sprintf(" reg %s [%3d:%3d] %s %s; //=%d'h%s"
, ($varref->{signed}?"signed":" ") , ($varref->{signed}?"signed":" ")
, ($varref->{val}->Size)-1+$VarAttrs{$var}{lsb}, , ($varref->{val}->Size)-1+$VarAttrs{$var}{lsb},
, $VarAttrs{$var}{lsb} , $VarAttrs{$var}{lsb}
@ -904,12 +904,19 @@ sub VPOW { # Power is a signed operation
$_[0]{val}=$o; $_[0]{val}=$o;
print "VV = $o\n"; print "VV = $o\n";
} }
sub VRANGE { #print "RANGE ",$_[1]->to_Hex,' ',$_[2]->to_Hex,' ',$_[3]->to_Hex," \n"; sub VRANGE {
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0),$_[3]->Word_Read(0), $_[4]); } #print "RANGE ",$_[1]->to_Hex,' ',$_[2]->to_Hex,' ',$_[3]->to_Hex," \n";
return VRANGE_CONST($_[0], $_[1], $_[2]->Word_Read(0),
$_[3]->Word_Read(0), $_[4]);
}
sub VBITSELP { sub VBITSELP {
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0)+$_[3]->Word_Read(0)-1, $_[2]->Word_Read(0), $_[4]); } return VRANGE_CONST($_[0], $_[1], $_[2]->Word_Read(0)+$_[3]->Word_Read(0)-1,
$_[2]->Word_Read(0), $_[4]);
}
sub VBITSELM { sub VBITSELM {
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0), $_[2]->Word_Read(0)-$_[3]->Word_Read(0)+1, $_[4]); } return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0),
$_[2]->Word_Read(0)-$_[3]->Word_Read(0)+1, $_[4]);
}
sub VRANGE_CONST { sub VRANGE_CONST {
# to, from, msb, lsb, variable_lsb_to_subtract # to, from, msb, lsb, variable_lsb_to_subtract
#print "RANGE ",$_[1]->to_Hex,' ',$_[2],' ',$_[3],' ',$_[4]," \n"; #print "RANGE ",$_[1]->to_Hex,' ',$_[2],' ',$_[3],' ',$_[4]," \n";