Fix hierarchical with parametrized instances under hier block (#6572)

src/V3HierBlock.cpp

@@ -356,18 +356,22 @@ class HierBlockUsageCollectVisitor final : public VNVisitorConst {
         if (modp->hierBlock()) m_childrenp.emplace_back(m_mod2vtx.at(modp));
     }
     void visit(AstVar* nodep) override {
-        if (m_modp && m_modp->hierBlock() && nodep->isIfaceRef() && !nodep->isIfaceParent()) {
+        if (!m_modp) return;
+        if (!m_modp->hierBlock()) return;
+        // Can't handle interface port on hier block
+        if (nodep->isIfaceRef() && !nodep->isIfaceParent()) {
             nodep->v3error("Modport cannot be used at the hierarchical block boundary");
         }
-        // Record overridden value parameter
+        // Record overridden value parameter of this hier block
         if (nodep->isGParam() && nodep->overriddenParam()) {
             UASSERT_OBJ(m_modp, nodep, "Value parameter not under module");
             m_params.push_back(nodep);
         }
     }
     void visit(AstParamTypeDType* nodep) override {
-        // Record type parameter
         UASSERT_OBJ(m_modp, nodep, "Type parameter not under module");
+        if (!m_modp->hierBlock()) return;
+        // Record type parameter of this hier block
         m_typeParams.push_back(nodep);
     }
 

test_regress/t/t_hier_parm_under.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
+test.clean_objs()
+
+test.compile(verilator_flags2=['--stats', '--hierarchical'])
+
+test.execute()
+
+test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 1)
+
+test.passes()

test_regress/t/t_hier_parm_under.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module sub;
+  /* verilator hier_block */
+  parametrized #(.ARG(1)) parametrized1();
+  parametrized #(.ARG(2)) parametrized2();
+
+  initial begin
+    if (parametrized1.ARG != 1) $stop;
+    if (parametrized2.ARG != 2) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule
+
+module parametrized #(parameter ARG=0);
+  // This is a parametrized non-hier block under a hier block
+endmodule
+
+module t;
+  sub sub();
+endmodule