Fix duplicate begin error broke in 3.840, bug548.

Changes

@@ -7,9 +7,11 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix double-deep parameter cell WIDTHs, bug541.  [Hiroki Honda]
 
-****  Fix imports under multiple instantiated cells, bug542. [Alex Solomatnikov]
+****  Fix imports under multiple instantiated cells, bug542.  [Alex Solomatnikov]
 
-****  Fix defparam in generate broke in 3.840, bug543. [Alex Solomatnikov]
+****  Fix defparam in generate broke in 3.840, bug543.  [Alex Solomatnikov]
+
+****  Fix duplicate begin error broke in 3.840, bug548.  [Alex Solomatnikov]
 
 
 * Verilator 3.840 2012/07/31 Beta

src/V3Begin.cpp

@@ -134,9 +134,11 @@ private:
 		    if (m_unnamedScope=="") m_unnamedScope = ident;
 		    else m_unnamedScope = m_unnamedScope + "__DOT__"+ident;
 		    // Create CellInline for dotted var resolution
-		    AstCellInline* inlinep = new AstCellInline(nodep->fileline(),
+		    if (!m_ftaskp) {
-							       m_unnamedScope, "__BEGIN__");
+			AstCellInline* inlinep = new AstCellInline(nodep->fileline(),
-		    m_modp->addInlinesp(inlinep);  // Must be parsed before any AstCells
+								   m_unnamedScope, "__BEGIN__");
+			m_modp->addInlinesp(inlinep);  // Must be parsed before any AstCells
+		    }
 		}
 	    }
 
@@ -184,6 +186,7 @@ private:
     virtual void visit(AstScopeName* nodep, AstNUser*) {
 	// If there's a %m in the display text, we add a special node that will contain the name()
 	// Similar code in V3Inline
+	if (nodep->user1SetOnce()) return;  // Don't double-add text's
 	if (m_namedScope != "") {
 	    // To keep correct visual order, must add before other Text's
 	    AstNode* afterp = nodep->scopeAttrp();

test_regress/t/t_func_begin2.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only --inline-mult 1"],
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+	 );
+
+ok(1);
+1;

test_regress/t/t_func_begin2.v

@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module init;
+   
+   task t1;
+      reg 		 ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz;
+      reg 		 ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz;
+      reg 		 da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn,   dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz;
+      begin : READER
+         $display ("Time: %0t  Instance: %m", $time);
+      end
+   endtask
+
+   task t2;
+      reg 		 ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz;
+      begin : READER
+         $display ("Time: %0t  Instance: %m", $time);
+      end
+   endtask
+endmodule
+
+module test();
+   init u_ram1();
+   init u_ram2();
+endmodule