Use vluint32_t where possible, aid bug204

include/verilated.cpp

@@ -179,8 +179,8 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
     }
 
     // +1 word as we may shift during normalization
-    uint32_t un[VL_MULS_MAX_WORDS+1]; // Fixed size, as MSVC++ doesn't allow [words] here
+    vluint32_t un[VL_MULS_MAX_WORDS+1]; // Fixed size, as MSVC++ doesn't allow [words] here
-    uint32_t vn[VL_MULS_MAX_WORDS+1]; // v normalized
+    vluint32_t vn[VL_MULS_MAX_WORDS+1]; // v normalized
 
     // Zero for ease of debugging and to save having to zero for shifts
     for (int i=0; i<words; i++) { un[i]=vn[i]=0; }
@@ -188,7 +188,7 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, boo
     // Algorithm requires divisor MSB to be set
     // Copy and shift to normalize divisor so MSB of vn[vw-1] is set
     int s = 31-VL_BITBIT_I(vmsbp1-1);  // shift amount (0...31)
-    uint32_t shift_mask = s ? 0xffffffff : 0;  // otherwise >> 32 won't mask the value
+    vluint32_t shift_mask = s ? 0xffffffff : 0;  // otherwise >> 32 won't mask the value
     for (int i = vw-1; i>0; i--) {
 	vn[i] = (rwp[i] << s) | (shift_mask & (rwp[i-1] >> (32-s)));
     }

include/verilatedsc.h

@@ -39,9 +39,9 @@
 #define VL_SC_BV_DATAP(bv) (VlScBvExposer::sp_datap(bv))
 class VlScBvExposer : public sc_bv_base {
 public:
-    static uint32_t* sp_datap(const sc_bv_base& base) {
+    static vluint32_t* sp_datap(const sc_bv_base& base) {
 	return static_cast<const VlScBvExposer*>(&base)->sp_datatp(); }
-    uint32_t* sp_datatp() const { return (uint32_t*)(m_data); }
+    vluint32_t* sp_datatp() const { return (vluint32_t*)(m_data); }
     // Above reads this protected element in sc_bv_base:
     //   sc_digit* m_data; // data array
 };

test_regress/t/t_dist_uint.pl

@@ -0,0 +1,39 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+use IO::File;
+
+my $root = "..";
+my $Debug;
+
+if (!-r "$root/.git") {
+    $Self->skip("Not in a git repository");
+} else {
+    ### Must trim output before and after our file list
+    #my $files = "*/*.c* */*.h test_regress/t/*.c* test_regress/t/*.h";
+    # src isn't clean, and probably doesn't need to be (yet?)
+    my $files = "include/*.c* include/*.h test_c/*.c* test_c/*.h  test_regress/t/*.c* test_regress/t/*.h";
+    my $cmd = "cd $root && fgrep -n int $files | sort";
+    print "C $cmd\n";
+    my $grep = `$cmd`;
+    my %names;
+    foreach my $line (split /\n/, $grep) {
+	next if $line !~ /uint\d+_t/;
+	next if $line =~ /vl[su]int\d+_t/;
+	next if $line =~ /typedef/;
+	next if $line =~ m!include/svdpi.h!;  # Not ours
+	$names{$1} = 1 if $line =~ /^([^:]+)/;
+    }
+    if (keys %names) {
+	$Self->error("Files with uint32*_t instead of vluint32s: ",join(' ',sort keys %names));
+    }
+}
+
+ok(1);
+1;

test_regress/t/t_extend_class_c.h

@@ -11,7 +11,7 @@ public:
     ~t_extend_class_c() {}
     // METHODS
     // This function will be called from a instance created in Verilog
-    inline uint32_t my_math(uint32_t in) {
+    inline vluint32_t my_math(vluint32_t in) {
 	return in+1;
     }
 };