Support void functions.

Fix "int" etc added in wrong keyword section in last commit.

Changes

@@ -8,6 +8,8 @@ indicates the contributor was also the author of the fix; Thanks!
 ***  Support byte, shortint, int, longint in variables, parameters and
      functions.
 
+***  Support void functions.
+
 * Verilator 3.720 2009/10/26
 
 **   Support little endian bit vectors ("reg [0:2] x;").

src/V3Ast.h

@@ -1205,11 +1205,13 @@ private:
     string	m_name;		// Name of task
     bool	m_taskPublic:1;	// Public task
     bool	m_didSigning:1;	// V3Signed completed; can skip iteration
+    bool	m_attrIsolateAssign:1;// User isolate_assignments attribute
 public:
     // Node that simply puts name into the output stream
     AstNodeFTask(FileLine* fileline, const string& name, AstNode* stmtsp)
 	: AstNode(fileline)
-	, m_name(name), m_taskPublic(false), m_didSigning(false) {
+	, m_name(name), m_taskPublic(false), m_didSigning(false)
+	, m_attrIsolateAssign(false) {
 	addNOp3p(stmtsp);
     }
     ASTNODE_BASE_FUNCS(NodeFTask)
@@ -1225,6 +1227,8 @@ public:
     bool	taskPublic() const { return m_taskPublic; }
     void	didSigning(bool flag) { m_didSigning=flag; }
     bool	didSigning() const { return m_didSigning; }
+    void	attrIsolateAssign(bool flag) { m_attrIsolateAssign = flag; }
+    bool	attrIsolateAssign() const { return m_attrIsolateAssign; }
 };
 
 struct AstNodeFTaskRef : public AstNode {

src/V3AstNodes.h

@@ -858,20 +858,15 @@ struct AstTask : public AstNodeFTask {
 };
 
 struct AstFunc : public AstNodeFTask {
-    bool	m_attrIsolateAssign:1;// User isolate_assignments attribute
-public:
     // A function inside a module
     AstFunc(FileLine* fl, const string& name, AstNode* stmtp, AstNode* fvarsp)
 	:AstNodeFTask(fl, name, stmtp) {
 	addNOp1p(fvarsp);
-	m_attrIsolateAssign = false;
     }
     ASTNODE_NODE_FUNCS(Func, FUNC)
     // op1 = Range output variable (functions only)
     AstNode*	fvarp() 	const { return op1p()->castNode(); }
     void addFvarp(AstNode* nodep) { addNOp1p(nodep); }
-    void	attrIsolateAssign(bool flag) { m_attrIsolateAssign = flag; }
-    bool	attrIsolateAssign() const { return m_attrIsolateAssign; }
 };
 
 struct AstTaskRef : public AstNodeFTaskRef {

src/V3ParseImp.h

@@ -61,10 +61,10 @@ struct V3ParseBisonYYSType {
 	AstCase*	casep;
 	AstCaseItem*	caseitemp;
 	AstConst*	constp;
-	AstFunc*	funcp;
 	AstModule*	modulep;
-	AstNodeSenItem*	senitemp;
 	AstNodeDType*	typep;
+	AstNodeFTask*	ftaskp;
+	AstNodeSenItem*	senitemp;
 	AstNodeVarRef*	varnodep;
 	AstParseRef*	parserefp;
 	AstPin*		pinp;

src/verilog.l

@@ -196,7 +196,6 @@ escid	\\[^ \t\f\r\n]+
   "buf"			{ FL; return yBUF; }
   "bufif0"		{ FL; return yBUFIF0; }
   "bufif1"		{ FL; return yBUFIF1; }
-  "byte"		{ FL; return yBYTE; }
   "case"		{ FL; return yCASE; }
   "casex"		{ FL; return yCASEX; }
   "casez"		{ FL; return yCASEZ; }
@@ -218,9 +217,7 @@ escid	\\[^ \t\f\r\n]+
   "initial"		{ FL; return yINITIAL; }
   "inout"		{ FL; return yINOUT; }
   "input"		{ FL; return yINPUT; }
-  "int"			{ FL; return yINT; }
   "integer"		{ FL; return yINTEGER; }
-  "longint"		{ FL; return yLONGINT; }
   "macromodule"		{ FL; return yMODULE; }
   "module"		{ FL; return yMODULE; }
   "nand"		{ FL; return yNAND; }
@@ -238,7 +235,6 @@ escid	\\[^ \t\f\r\n]+
   "reg"			{ FL; return yREG; }
   "repeat"		{ FL; return yREPEAT; }
   "scalared"		{ FL; return ySCALARED; }
-  "shortint"		{ FL; return ySHORTINT; }
   "specify"		{ FL; return ySPECIFY; }
   "specparam"		{ FL; return ySPECPARAM; }
   "supply0"		{ FL; return ySUPPLY0; }
@@ -360,23 +356,28 @@ escid	\\[^ \t\f\r\n]+
   "$onehot"		{ FL; return yD_ONEHOT; }
   "$onehot0"		{ FL; return yD_ONEHOT0; }
   "$warning"		{ FL; return yD_WARNING; }
-  /*     Keywords */
+  /*     SV2005 Keywords */
   "always_comb"		{ FL; return yALWAYS; }
   "always_ff"		{ FL; return yALWAYS; }
   "always_latch"	{ FL; return yALWAYS; }
   "bit"			{ FL; return yBIT; }
+  "byte"		{ FL; return yBYTE; }
   "clocking"		{ FL; return yCLOCKING; }
   "do"			{ FL; return yDO; }
   "endclocking"		{ FL; return yENDCLOCKING; }
   "endproperty"		{ FL; return yENDPROPERTY; }
   "final"		{ FL; return yFINAL; }
   "iff"			{ FL; return yIFF; }
+  "int"			{ FL; return yINT; }
   "logic"		{ FL; return yLOGIC; }
+  "longint"		{ FL; return yLONGINT; }
   "priority"		{ FL; return yPRIORITY; }
+  "shortint"		{ FL; return ySHORTINT; }
   "static"		{ FL; return ySTATIC; }
   "timeprecision"	{ FL; return yTIMEPRECISION; }
   "timeunit"		{ FL; return yTIMEUNIT; }
   "unique"		{ FL; return yUNIQUE; }
+  "void"		{ FL; return yVOID; }
   /*     Generic unsupported warnings */
   /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
   "$root"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
@@ -446,7 +447,6 @@ escid	\\[^ \t\f\r\n]+
   "typedef"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "var"			{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "virtual"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
-  "void"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "wait_order"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "wildcard"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "with"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }

src/verilog.y

@@ -278,6 +278,7 @@ class AstSenTree;
 %token<fl>		yUNIQUE		"unique"
 %token<fl>		yUNSIGNED	"unsigned"
 %token<fl>		yVECTORED	"vectored"
+%token<fl>		yVOID		"void"
 %token<fl>		yWHILE		"while"
 %token<fl>		yWIRE		"wire"
 %token<fl>		yXNOR		"xnor"
@@ -1743,16 +1744,15 @@ list_of_argumentsE<nodep>:	// IEEE: [list_of_arguments]
 	//UNSUP empty arguments with just ,,
 	;
 
-task_declaration<taskp>:	// ==IEEE: task_declaration
+task_declaration<ftaskp>:	// ==IEEE: task_declaration
 		yTASK lifetimeE taskId tfGuts yENDTASK endLabelE
 			{ $$ = $3; $$->addStmtsp($4); SYMP->popScope($$); }
 	;
 
-function_declaration<funcp>:	// IEEE: function_declaration + function_body_declaration
+function_declaration<ftaskp>:	// IEEE: function_declaration + function_body_declaration
 	 	yFUNCTION lifetimeE funcId funcIsolateE tfGuts yENDFUNCTION endLabelE
-			{ $$ = $3; $$->attrIsolateAssign($4); $$->addStmtsp($5);
+			{ $$ = $3; $3->attrIsolateAssign($4); $$->addStmtsp($5);
 			  SYMP->popScope($$); }
-	//UNSUP: Generic function return types
 	;
 
 funcIsolateE<cint>:
@@ -1777,25 +1777,27 @@ taskId<taskp>:
 			  SYMP->pushNewUnder($$, NULL); }
 	;
 
-funcId<funcp>:			// IEEE: function_data_type_or_implicit + part of function_body_declaration
+funcId<ftaskp>:			// IEEE: function_data_type_or_implicit + part of function_body_declaration
 	//			// IEEE: function_data_type_or_implicit must be expanded here to prevent conflict
 	//			// function_data_type expanded here to prevent conflicts with implicit_type:empty vs data_type:ID
 		/**/			tfIdScoped
-			{ $$ = new AstFunc ($<fl>1,*$<strp>1,NULL,NULL);
+			{ $$ = new AstFunc ($<fl>1,*$<strp>1,NULL,
-			  $$->addFvarp(new AstBasicDType($$->fileline(), LOGIC_IMPLICIT, NULL));
+					    new AstBasicDType($<fl>1, LOGIC_IMPLICIT, NULL));
 			  SYMP->pushNewUnder($$, NULL); }
 	|	signingE rangeList	tfIdScoped
-			{ $$ = new AstFunc ($<fl>3,*$<strp>3,NULL,NULL);
+			{ $$ = new AstFunc ($<fl>3,*$<strp>3,NULL,
-			  $$->addFvarp(new AstBasicDType($$->fileline(), LOGIC_IMPLICIT, $2, $1));
+					    new AstBasicDType($<fl>3, LOGIC_IMPLICIT, $2, $1));
 			  SYMP->pushNewUnder($$, NULL); }
 	|	signing			tfIdScoped
-			{ $$ = new AstFunc ($<fl>2,*$<strp>2,NULL,NULL);
+			{ $$ = new AstFunc ($<fl>2,*$<strp>2,NULL,
-			  $$->addFvarp(new AstBasicDType($$->fileline(), LOGIC_IMPLICIT, NULL, $1));
+					    new AstBasicDType($<fl>2, LOGIC_IMPLICIT, NULL, $1));
 			  SYMP->pushNewUnder($$, NULL); }
-	//UNSUP	yVOID			tfIdScoped	{ UNSUP }
 	|	data_type		tfIdScoped
-			{ $$ = new AstFunc ($<fl>2,*$<strp>2,NULL,NULL);
+			{ $$ = new AstFunc ($<fl>2,*$<strp>2,NULL,$1);
-			  $$->addFvarp($1);
+			  SYMP->pushNewUnder($$, NULL); }
+	//			// To verilator tasks are the same as void functions (we separately detect time passing)
+	|	yVOID			tfIdScoped
+			{ $$ = new AstTask ($<fl>2,*$<strp>2,NULL);
 			  SYMP->pushNewUnder($$, NULL); }
 	;
 

test_regress/t/t_func.v

@@ -7,6 +7,7 @@ module t;
    reg [2:0] value;
    reg [31:0] global;
    reg [31:0] vec [1:0];
+   reg [31:0] n;
 
    initial begin
       global = 1;
@@ -42,6 +43,10 @@ module t;
 
       incr(vec[2],vec[0],vec[2]);  // Reading/Writing past end of vector!
 
+      n=1;
+      nil();
+      if (n !== 10) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end
@@ -112,6 +117,10 @@ module t;
       q = nil_func(a, b);
    endtask
 
+   function void nil;
+      n = 10;
+   endfunction
+
    function [31:0] nil_func;
       input [31:0] fa;
       input [31:0] fb;