Support covergroup extends, etc. (#6160)

src/verilog.y

@@ -6822,21 +6822,38 @@ covergroup_declaration<nodep>:  // ==IEEE: covergroup_declaration
         |       covergroup_declarationFront '(' tf_port_listE ')'
         /*cont*/    coverage_eventE ';' coverage_spec_or_optionListE
         /*cont*/    yENDGROUP endLabelE
-                        { $$ = $1;
+                        { AstFunc* const newp = new AstFunc{$<fl>1, "new", nullptr, nullptr};
+                          newp->classMethod(true);
+                          newp->isConstructor(true);
+                          newp->dtypep($1->dtypep());
+                          newp->addStmtsp($3);
+                          $1->addMembersp(newp);
+                          $$ = $1;
                           GRAMMARP->endLabel($<fl>9, $1, $9); }
-        //                      // IEEE 1800-2023 added:
+        ;
-        |       covergroup_declarationFront yEXTENDS idAny/*covergroup_identifier*/
+
-        /*cont*/    ';' coverage_spec_or_optionListE
+covergroup_extendsE<fl>:  // IEEE: Part of covergroup_declaration
-        /*cont*/    yENDGROUP endLabelE
+                /* empty */                             { $$ = nullptr; }
-                        { $$ = $1;
+        |       yEXTENDS                                { $$ = $1; }
-                          GRAMMARP->endLabel($<fl>7, $1, $7); }
         ;
 
 covergroup_declarationFront<classp>:  // IEEE: part of covergroup_declaration
-                yCOVERGROUP idAny
+                yCOVERGROUP covergroup_extendsE idAny
-                        { $$ = new AstClass{$<fl>2, *$2, PARSEP->libname()};
+                        {
+                          $$ = new AstClass{$<fl>3, *$3, PARSEP->libname()};
+
+                          AstFunc* const sample = new AstFunc{$<fl>1, "sample", nullptr, nullptr};
+                          sample->classMethod(true);
+                          sample->dtypep(sample->findVoidDType());
+                          $$->addMembersp(sample);
+
+                          AstFunc* const getCoverage = new AstFunc{$<fl>1, "get_coverage", nullptr, nullptr};
+                          getCoverage->classMethod(true);
+                          getCoverage->dtypep(getCoverage->findVoidDType());
+                          $$->addMembersp(getCoverage);
+
                           BBCOVERIGN($<fl>1, "Ignoring unsupported: covergroup"); }
-        ;
+                ;
 
 cgexpr<nodeExprp>:  // IEEE-2012: covergroup_expression, before that just expression
                 expr                                    { $$ = $1; }
@@ -7006,7 +7023,7 @@ cross_itemList<nodep>:  // IEEE: part of list_of_cross_items
         ;
 
 cross_item<nodep>:  // ==IEEE: cross_item
-                idAny/*cover_point_identifier or variable_identifier*/  { $$ = nullptr; /*UNSUP*/ }
+                idDotted/*cover_point_identifier or variable_identifier*/  { $1->deleteTree(); $$ = nullptr; /*UNSUP*/ }
         ;
 
 cross_body<nodep>:  // ==IEEE: cross_body
@@ -7552,7 +7569,12 @@ class_item<nodep>:                      // ==IEEE: class_item
         |       class_declaration                       { $$ = $1; }
         |       timeunits_declaration                   { $$ = $1; }
         |       covergroup_declaration
-                        { $$ = nullptr; BBCOVERIGN($1, "Ignoring unsupported: covergroup within class"); }
+                        {
+                          const string cgName = $1->name();
+                          $1->name("__vlAnonCG_" + cgName);
+                          AstVar* const newp = new AstVar{$<fl>1, VVarType::VAR, cgName, VFlagChildDType{}, new AstRefDType($<fl>1, $1->name())};
+                          $$ = addNextNull($1, newp);
+                        }
         //                      // local_parameter_declaration under parameter_declaration
         |       parameter_declaration ';'               { $$ = $1; }
         |       ';'                                     { $$ = nullptr; }

test_regress/t/t_covergroup_args.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile()
+
+test.passes()

test_regress/t/t_covergroup_args.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+/* verilator lint_off COVERIGN */
+module t;
+    covergroup cgArgs(int var1, int var2=42);
+
+    endgroup
+
+    cgArgs cov1 = new(69, 77);
+    cgArgs cov2 = new(69);
+    function x();
+        cov1.sample();
+        cov2.get_coverage();
+    endfunction;
+endmodule

test_regress/t/t_covergroup_extends.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile()
+
+test.passes()

test_regress/t/t_covergroup_extends.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+/* verilator lint_off COVERIGN */
+module t;
+    class base;
+        enum {red, green, blue} color;
+        covergroup g1 (bit [3:0] a) with function sample(bit b);
+            option.weight       = 10;
+            option.per_instance = 1;
+            coverpoint a;
+            coverpoint b;
+            c: coverpoint color;
+        endgroup
+        function new();
+            g1 = new(0);
+        endfunction
+    endclass
+
+    class derived extends base;
+        bit d;
+        covergroup extends g1;
+            option.weight = 1;  // overrides the weight from base g1
+                                // uses per_instance = 1 from base g1
+            c: coverpoint color // overrides the c coverpoint in base g1
+            {
+                ignore_bins ignore = {blue};
+            }
+            coverpoint d;       // adds new coverpoint
+            cross a, d;         // crosses new coverpoint with inherited one
+        endgroup :g1
+        function new();
+            super.new();
+        endfunction
+    endclass
+endmodule

test_regress/t/t_covergroup_extends_newfirst.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile()
+
+test.passes()

test_regress/t/t_covergroup_extends_newfirst.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+/* verilator lint_off COVERIGN */
+module t;
+    class base;
+        function new();
+            g1 = new(0);
+        endfunction
+        enum {red, green, blue} color;
+        covergroup g1 (bit [3:0] a) with function sample(bit b);
+            option.weight       = 10;
+            option.per_instance = 1;
+            coverpoint a;
+            coverpoint b;
+            c: coverpoint color;
+        endgroup
+    endclass
+
+    class derived extends base;
+        bit d;
+        function new();
+            super.new();
+        endfunction
+        covergroup extends g1;
+            option.weight = 1;  // overrides the weight from base g1
+                                // uses per_instance = 1 from base g1
+            c: coverpoint color // overrides the c coverpoint in base g1
+            {
+                ignore_bins ignore = {blue};
+            }
+            coverpoint d;       // adds new coverpoint
+            cross a, d;         // crosses new coverpoint with inherited one
+        endgroup :g1
+    endclass
+endmodule

test_regress/t/t_covergroup_func_override_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_covergroup_func_override_bad.v:10:5: syntax error, unexpected function
+   10 |     function sample();
+      |     ^~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to

test_regress/t/t_covergroup_func_override_bad.py

@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if test.vlt_all:
+    test.lint(fails=True, expect_filename=test.golden_filename)
+else:
+    test.compile(nc_flags2=["-coverage", "functional"])
+    test.execute()
+
+test.passes()

test_regress/t/t_covergroup_func_override_bad.v

@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+/* verilator lint_off COVERIGN */
+module t();
+    covergroup cg;
+    function sample();
+
+    endfunction
+    function get_coverage();
+
+    endfunction
+    endgroup
+endmodule

test_regress/t/t_covergroup_in_class.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile()
+
+test.passes()

test_regress/t/t_covergroup_in_class.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+/* verilator lint_off COVERIGN */
+class myClass;
+    covergroup embeddedCg;
+
+    endgroup
+
+    function new();
+        embeddedCg = new();
+        embeddedCg.sample();
+        embeddedCg.get_coverage();
+    endfunction
+endclass

test_regress/t/t_covergroup_in_class_colliding.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile()
+
+test.passes()

test_regress/t/t_covergroup_in_class_colliding.v

@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+/* verilator lint_off COVERIGN */
+class myClass;
+    covergroup embeddedCg;
+
+    endgroup
+
+    function new();
+        embeddedCg = new();
+        embeddedCg.sample();
+        embeddedCg.get_coverage();
+    endfunction
+endclass
+
+class secondClass;
+    covergroup embeddedCg;
+
+    endgroup
+
+    function new();
+        embeddedCg = new();
+        embeddedCg.sample();
+        embeddedCg.get_coverage();
+    endfunction
+endclass

test_regress/t/t_covergroup_in_class_duplicate_bad.out

@@ -0,0 +1,8 @@
+%Error: t/t_covergroup_in_class_duplicate_bad.v:13:16: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg'
+   13 |     covergroup embeddedCg;
+      |                ^~~~~~~~~~
+        t/t_covergroup_in_class_duplicate_bad.v:9:16: ... Location of original declaration
+    9 |     covergroup embeddedCg;
+      |                ^~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to

test_regress/t/t_covergroup_in_class_duplicate_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_covergroup_in_class_duplicate_bad.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+/* verilator lint_off COVERIGN */
+class myClass;
+    covergroup embeddedCg;
+
+    endgroup
+
+    covergroup embeddedCg;
+
+    endgroup
+endclass

test_regress/t/t_covergroup_new_override_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_covergroup_new_override_bad.v:10:5: syntax error, unexpected function
+   10 |     function new();
+      |     ^~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to

test_regress/t/t_covergroup_new_override_bad.py

@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if test.vlt_all:
+    test.lint(fails=True, expect_filename=test.golden_filename)
+else:
+    test.compile(nc_flags2=["-coverage", "functional"])
+    test.execute()
+
+test.passes()

test_regress/t/t_covergroup_new_override_bad.v

@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+/* verilator lint_off COVERIGN */
+module t();
+    covergroup cg;
+    function new();
+
+    endfunction
+    endgroup
+endmodule

test_regress/t/t_covergroup_unsup.out

@@ -385,28 +385,21 @@
   136 |       cross a, b {
       |       ^~~~~
 %Warning-COVERIGN: t/t_covergroup_unsup.v:154:4: Ignoring unsupported: covergroup
-  154 |    covergroup cg_more extends cg_empty;
+  154 |    covergroup cgArgs(int cg_lim);
       |    ^~~~~~~~~~
-%Warning-COVERIGN: t/t_covergroup_unsup.v:157:4: Ignoring unsupported: covergroup
+%Warning-COVERIGN: t/t_covergroup_unsup.v:161:7: Ignoring unsupported: covergroup
-  157 |    covergroup cg_args(int cg_lim);
+  161 |       covergroup cov1 @m_z;
-      |    ^~~~~~~~~~
-%Warning-COVERIGN: t/t_covergroup_unsup.v:164:7: Ignoring unsupported: covergroup
-  164 |       covergroup cov1 @m_z;
       |       ^~~~~~~~~~
-%Warning-COVERIGN: t/t_covergroup_unsup.v:164:23: Ignoring unsupported: coverage clocking event
+%Warning-COVERIGN: t/t_covergroup_unsup.v:161:23: Ignoring unsupported: coverage clocking event
-  164 |       covergroup cov1 @m_z;
+  161 |       covergroup cov1 @m_z;
       |                       ^
-%Warning-COVERIGN: t/t_covergroup_unsup.v:165:10: Ignoring unsupported: coverpoint
+%Warning-COVERIGN: t/t_covergroup_unsup.v:162:10: Ignoring unsupported: coverpoint
-  165 |          coverpoint m_x;
+  162 |          coverpoint m_x;
       |          ^~~~~~~~~~
-%Warning-COVERIGN: t/t_covergroup_unsup.v:166:10: Ignoring unsupported: coverpoint
+%Warning-COVERIGN: t/t_covergroup_unsup.v:163:10: Ignoring unsupported: coverpoint
-  166 |          coverpoint m_y;
+  163 |          coverpoint m_y;
       |          ^~~~~~~~~~
-%Warning-COVERIGN: t/t_covergroup_unsup.v:164:18: Ignoring unsupported: covergroup within class
+%Warning-COVERIGN: t/t_covergroup_unsup.v:171:7: Ignoring unsupported: covergroup
-  164 |       covergroup cov1 @m_z;
+  171 |       covergroup extends cg_empty;
-      |                  ^~~~
+      |       ^~~~~~~~~~
-%Error: t/t_covergroup_unsup.v:169:23: Can't find definition of variable: 'cov1'
-  169 |       function new(); cov1 = new; endfunction
-      |                       ^~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_covergroup_unsup.v

@@ -151,10 +151,7 @@ module t (/*AUTOARG*/
       }
    endgroup
 
-   covergroup cg_more extends cg_empty;
+   covergroup cgArgs(int cg_lim);
-   endgroup
-
-   covergroup cg_args(int cg_lim);
    endgroup
 
    class CgCls;
@@ -170,10 +167,15 @@ module t (/*AUTOARG*/
 `endif
    endclass
 
+   class CgEmb;
+      covergroup extends cg_empty;
+      endgroup
+   endclass
+
    always @(posedge clk) begin
-      cg_more cov1 = new;
+      cg_empty cov1 = new;
 `ifndef T_COVERGROUP_UNSUP_IGN
-      cg_args cov2 = new(2);
+      cgArgs cov2 = new(2);
 `endif
       if (cyc == 10) begin
          $write("*-* All Finished *-*\n");