Support "`default_nettype none|wire".

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Support "break", "continue", "return".
 
+**** Support "`default_nettype none|wire".  [Dominic Plunkett]
+
 **** Skip SystemC tests if not installed.  [Iztok Jeras]
 
 **** Fix make uninstall, bug216.  [Iztok Jeras]

src/V3Error.h

@@ -44,6 +44,7 @@ public:
 	// Boolean information we track per-line, but aren't errors
 	I_COVERAGE,	// Coverage is on/off from /*verilator coverage_on/off*/
 	I_TRACING,	// Tracing is on/off from /*verilator tracing_on/off*/
+	I_DEF_NETTYPE_WIRE,  // `default_nettype is WIRE (false=NONE)
 	// Error codes:
 	E_MULTITOP,	// Error: Multiple top level modules
 	E_TASKNSVAR,	// Error: Task I/O not simple
@@ -91,7 +92,7 @@ public:
 	    // Leading spaces indicate it can't be disabled.
 	    " MIN", " SUPPRESS", " INFO", " FATAL", " FATALSRC", " ERROR",
 	    // Boolean
-	    " I_COVERAGE", " I_TRACING",
+	    " I_COVERAGE", " I_TRACING", " I_DEF_NETTYPE_WIRE",
 	    // Errors
 	    "MULTITOP", "TASKNSVAR", "BLKLOOPINIT",
 	    // Warnings

src/V3Link.cpp

@@ -185,7 +185,13 @@ private:
 	// Create implicit after warning
 	if (linkVarName(forrefp)) { forrefp=NULL; return; }
 	if (!forrefp->varp()) {
-	    if (!noWarn) forrefp->v3warn(IMPLICIT,"Signal definition not found, creating implicitly: "<<forrefp->prettyName());
+	    if (!noWarn) {
+		if (forrefp->fileline()->warnIsOff(V3ErrorCode::I_DEF_NETTYPE_WIRE)) {
+		    forrefp->v3error("Signal definition not found, and implicit disabled with `default_nettype: "<<forrefp->prettyName());
+		} else {
+		    forrefp->v3warn(IMPLICIT,"Signal definition not found, creating implicitly: "<<forrefp->prettyName());
+		}
+	    }
 	    AstVar* newp = new AstVar (forrefp->fileline(), AstVarType::WIRE,
 				       forrefp->name(), AstLogicPacked(), 1);
 

src/verilog.l

@@ -863,7 +863,9 @@ escid	\\[^ \t\f\r\n]+
   "`autoexpand_vectornets"		{ } // Verilog-XL compatibility
   "`celldefine"				{ PARSEP->inCellDefine(true); }
   "`default_decay_time"{ws}+[^\n\r]*	{ } // Verilog spec - delays only
-  "`default_nettype"{ws}+[a-zA-Z0-9]*	{ yyerrorf("Unsupported: Verilog 2001 directive not implemented: %s",yytext); } // Verilog 2001
+  "`default_nettype"{ws}+"wire"		{ PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE,true); }
+  "`default_nettype"{ws}+"none"		{ PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE,false); }
+  "`default_nettype"{ws}+[a-zA-Z0-9]*	{ yyerrorf("Unsupported: `default_nettype of other than none or wire: %s",yytext); }
   "`default_trireg_strength"{ws}+[^\n\r]*	{ yyerrorf("Unsupported: Verilog optional directive not implemented: %s",yytext); }
   "`delay_mode_distributed"		{ } // Verilog spec - delays only
   "`delay_mode_path"			{ } // Verilog spec - delays only
@@ -888,7 +890,7 @@ escid	\\[^ \t\f\r\n]+
   "`psl"				{ if (PARSEP->optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
   "`remove_gatenames"			{ } // Verilog-XL compatibility
   "`remove_netnames"			{ } // Verilog-XL compatibility
-  "`resetall"				{ }
+  "`resetall"				{ PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE,true); } // Rest handled by preproc
   "`suppress_faults"			{ } // Verilog-XL compatibility
   "`timescale"{ws}+[^\n\r]*		{ } // Verilog spec - not supported
 

test_regress/t/t_lint_implicit_def_bad.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+'%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:\d+: Signal definition not found, creating implicitly: imp_warn
+%Warning-IMPLICIT: Use "/\* verilator lint_off IMPLICIT \*/" and lint_on around source to disable this message.
+%Error: t/t_lint_implicit_def_bad.v:\d+: Signal definition not found, and implicit disabled with `default_nettype: imp_err
+%Error: Exiting due to.*',
+	 ) if $Self->{v3};
+
+ok(1);
+1;
+

test_regress/t/t_lint_implicit_def_bad.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (a,z);
+   input a;
+   output z;
+
+   assign imp_warn = 1'b1;
+   // verilator lint_off IMPLICIT
+   assign imp_ok = 1'b1;
+
+`default_nettype none
+   assign imp_err = 1'b1;
+
+`default_nettype wire
+   assign imp_ok2 = 1'b1;
+
+`default_nettype none
+`resetall
+   assign imp_ok3 = 1'b1;
+endmodule