Fix "always @ (* )", bug403, bug404.

Changes

@@ -3,6 +3,11 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.823***
+
+***  Fix "always @ (* )", bug403, bug404.  [Walter Lavino]
+
+
 * Verilator 3.822 2011/10/20
 
 ***  Support $ceil, $floor, etc.  [Alex Solomatnikov]

src/verilog.l

@@ -859,8 +859,9 @@ word	[a-zA-Z0-9_]+
 
   /************************************************************************/
   /* Attributes */
+  /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
 <V95,V01,V05,S05,S09>{
-    "(*"/{ws}*[^)]	{ yymore(); yy_push_state(ATTRMODE); }	// Doesn't match (*)
+    "(*"({ws}|{crnl})*({id}|{escid})	{ yymore(); yy_push_state(ATTRMODE); }	// Doesn't match (*), but (* attr_spec
 }
 
   /************************************************************************/

test_regress/t/t_attr_parenstar.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_attr_parenstar.v

@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   always @(*) begin
+      if (clk) begin end
+   end
+
+   always @(* ) begin
+      if (clk) begin end
+   end
+
+   // Not legal in some simulators, legal in others
+//   always @(* /*cmt*/ ) begin
+//      if (clk) begin end
+//   end
+
+   // Not legal in some simulators, legal in others
+//   always @(* // cmt
+//	    ) begin
+//      if (clk) begin end
+//   end
+
+   always @ (*
+	     ) begin
+      if (clk) begin end
+   end
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule