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Fix to be in verilog 2005, bug1319. 

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
James Hutchinson 2018-06-08 08:01:22 -04:00 committed by Wilson Snyder
parent 94c8064798
commit f0ed4346b2
2 changed files with 4 additions and 1 deletions
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@ -14,6 +14,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix parsing error on bad missing #, bug1308. [Dan Kirkham] **** Fix parsing error on bad missing #, bug1308. [Dan Kirkham]
**** Fix $clog2 to be in verilog 2005, bug1319. [James Hutchinson]
* Verilator 3.922 2018-03-17 * Verilator 3.922 2018-03-17

3
src/verilog.l
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@ -422,6 +422,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Verilog 2005 */ /* Verilog 2005 */
<V05,S05,S09,S12,S17,SAX>{ <V05,S05,S09,S12,S17,SAX>{
/* System Tasks */
"$clog2" { FL; return yD_CLOG2; }
/* Keywords */ /* Keywords */
"uwire" { FL; return yWIRE; } "uwire" { FL; return yWIRE; }
} }
@ -430,7 +432,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
<S05,S09,S12,S17,SAX>{ <S05,S09,S12,S17,SAX>{
/* System Tasks */ /* System Tasks */
"$bits" { FL; return yD_BITS; } "$bits" { FL; return yD_BITS; }
"$clog2" { FL; return yD_CLOG2; }
"$countones" { FL; return yD_COUNTONES; } "$countones" { FL; return yD_COUNTONES; }
"$dimensions" { FL; return yD_DIMENSIONS; } "$dimensions" { FL; return yD_DIMENSIONS; }
"$error" { FL; return yD_ERROR; } "$error" { FL; return yD_ERROR; }