Fix CASEINCOMPLETE to not warn on `unique0 case` (#7647).

Fixes #7647.
This commit is contained in:
Wilson Snyder 2026-05-23 19:56:28 -04:00
parent adddec6547
commit f0c569ab0d
4 changed files with 17 additions and 5 deletions

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@ -83,6 +83,7 @@ Verilator 5.049 devel
* Fix force determinism (#7620) (#7637). [Artur Bieniek, Antmicro Ltd.]
* Fix reference counting for modport task references (#7628). [Nick Brereton]
* Fix implicit conversions of VlWide (#7642). [Geza Lore, Testorrent USA, Inc.]
* Fix CASEINCOMPLETE to not warn on `unique0 case` (#7647).
Verilator 5.048 2026-04-26

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@ -382,6 +382,9 @@ List Of Warnings
non-enumerated values (IEEE 1800-2023 12.5.3). Verilator checks that
illegal values are not hit, unless :vlopt:`--no-assert-case` was used.
Unique0 case statements will never cause this warning. (Although unique0
should be avoided in synthesizable code as may result in latch behavior.)
Ignoring this warning will only suppress the lint check; it will
simulate correctly.

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@ -178,8 +178,10 @@ class CaseVisitor final : public VNVisitor {
for (uint32_t i = 0; i < numCases; ++i) {
if ((i & mask) == val) {
if (!m_valueItem[i]) {
nodep->v3warn(CASEINCOMPLETE, "Enum item " << itemp->prettyNameQ()
<< " not covered by case\n");
if (!nodep->unique0Pragma())
nodep->v3warn(CASEINCOMPLETE, "Enum item "
<< itemp->prettyNameQ()
<< " not covered by case\n");
m_caseIncomplete = true;
return false; // enum has uncovered value by case items
}
@ -310,9 +312,10 @@ class CaseVisitor final : public VNVisitor {
} else {
for (uint32_t i = 0; i < numCases; ++i) {
if (!m_valueItem[i]) { // has uncovered case
nodep->v3warn(CASEINCOMPLETE, "Case values incompletely covered "
"(example pattern 0x"
<< std::hex << i << ")");
if (!nodep->unique0Pragma())
nodep->v3warn(CASEINCOMPLETE, "Case values incompletely covered "
"(example pattern 0x"
<< std::hex << i << ")");
m_caseIncomplete = true;
m_caseNoOverlapsAllCovered = false;
return false;

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@ -14,5 +14,10 @@ module t (
2'b10: ;
2'b11: ;
endcase
unique0 case (i) // No warning
2'b00: ;
endcase
end
endmodule