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verilator
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Merge from master.

This commit is contained in:
Wilson Snyder 2018-02-27 07:24:31 -05:00
parent 597d28b505 a7a790416e
commit f0ba17a19b
32 changed files with 421 additions and 158 deletions
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6
Changes
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@ -13,6 +13,12 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 3.921 devel
*** Support trig functions ($sin() etc), bug1281. [Patrick Stewart]
**** Fix GCC 8.0 issues, bug1273.
**** Fix pullup/pulldowns on bit selects, bug1274. [Rob Stoddard]
* Verilator 3.920 2018-02-01

2
configure.ac
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@ -77,6 +77,8 @@ AC_PROG_CXX
AC_PROG_INSTALL
AC_LANG_PUSH(C++)
cxx_version=$($CXX --version | head -1)
AC_MSG_RESULT([compiler is $CXX --version = $cxx_version])
AC_MSG_CHECKING([that C++ compiler can compile simple program])
AC_RUN_IFELSE(
[AC_LANG_SOURCE([int main() { return 0; }])],

2
include/verilated.cpp
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@ -1529,6 +1529,8 @@ void Verilated::flushCb(VerilatedVoidCb cb) VL_MT_SAFE {
void Verilated::flushCall() VL_MT_SAFE {
VerilatedLockGuard guard(m_mutex);
if (s_flushCb) (*s_flushCb)();
fflush(stderr);
fflush(stdout);
}
void Verilated::commandArgs(int argc, const char** argv) VL_MT_SAFE {

2
include/verilated_heavy.h
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@ -66,7 +66,7 @@ extern IData VL_FOPEN_NI(const std::string& filename, IData mode) VL_MT_SAFE;
extern void VL_READMEM_N(bool hex, int width, int depth, int array_lsb, int fnwords,
const std::string& ofilename, void* memp, IData start, IData end) VL_MT_SAFE;
extern IData VL_SSCANF_INX(int lbits, const std::string& ld, const char* formatp, ...) VL_MT_SAFE;
extern void VL_SFORMAT_X(int obits_ignored, std::string &output, const char* formatp, ...) VL_MT_SAFE;
extern void VL_SFORMAT_X(int obits_ignored, std::string& output, const char* formatp, ...) VL_MT_SAFE;
extern std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE;
extern IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rdp) VL_MT_SAFE;
inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, IData& rdr) VL_MT_SAFE {

2
include/verilated_imp.h
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@ -54,7 +54,7 @@ class VerilatedMsg {
public:
// TYPES
struct Cmp {
bool operator() (const VerilatedMsg& a, const VerilatedMsg& b) {
bool operator() (const VerilatedMsg& a, const VerilatedMsg& b) const {
return a.trainId() < b.trainId(); }
};
private:

2
include/verilated_vpi.cpp
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@ -459,7 +459,7 @@ public:
m_errorInfo.level = level;
return this;
}
void setMessage(std::string file, PLI_INT32 line, std::string message, ...) {
void setMessage(std::string file, PLI_INT32 line, const std::string& message, ...) {
static VL_THREAD_LOCAL std::string filehold;
va_list args;
va_start(args, message);

2
src/V3Ast.h
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@ -1296,7 +1296,7 @@ public:
static AstNode* addNextNull(AstNode* nodep, AstNode* newp); // Returns nodep, adds newp (maybe NULL) to end of nodep's list
inline AstNode* addNext(AstNode* newp) { return addNext(this, newp); }
inline AstNode* addNextNull(AstNode* newp) { return addNextNull(this, newp); }
void addNextHere(AstNode* newp); // Adds after speced node
void addNextHere(AstNode* newp); // Insert newp at this->nextp
void addPrev(AstNode* newp) { replaceWith(newp); newp->addNext(this); }
void addHereThisAsNext(AstNode* newp); // Adds at old place of this, this becomes next
void replaceWith(AstNode* newp); // Replace current node in tree with new node

248
src/V3AstNodes.h
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@ -3947,94 +3947,175 @@ public:
AstNode* filep() const { return lhsp(); }
};
class AstCeilD : public AstNodeUniop {
class AstNodeSystemUniop : public AstNodeUniop {
public:
AstCeilD(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
dtypeSetDouble(); }
ASTNODE_NODE_FUNCS(CeilD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) {
out.setDouble(ceil(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$ceil(%l)"; }
virtual string emitC() { return "ceil(%li)"; }
AstNodeSystemUniop(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
dtypeSetDouble(); }
virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return false;}
virtual bool sizeMattersLhs() {return false;}
virtual int instrCount() const { return instrCountDoubleTrig(); }
virtual int instrCount() const { return instrCountDoubleTrig(); }
virtual bool doubleFlavor() const { return true; }
};
class AstExpD : public AstNodeUniop {
class AstLogD : public AstNodeSystemUniop {
public:
AstExpD(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
dtypeSetDouble(); }
ASTNODE_NODE_FUNCS(ExpD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) {
out.setDouble(exp(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$exp(%l)"; }
virtual string emitC() { return "exp(%li)"; }
virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return false;}
virtual bool sizeMattersLhs() {return false;}
virtual int instrCount() const { return instrCountDoubleTrig(); }
virtual bool doubleFlavor() const { return true; }
};
class AstFloorD : public AstNodeUniop {
public:
AstFloorD(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
dtypeSetDouble(); }
ASTNODE_NODE_FUNCS(FloorD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) {
out.setDouble(floor(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$floor(%l)"; }
virtual string emitC() { return "floor(%li)"; }
virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return false;}
virtual bool sizeMattersLhs() {return false;}
virtual int instrCount() const { return instrCountDoubleTrig(); }
virtual bool doubleFlavor() const { return true; }
};
class AstLogD : public AstNodeUniop {
public:
AstLogD(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
dtypeSetDouble(); }
AstLogD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(LogD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) {
out.setDouble(log(lhs.toDouble())); }
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(log(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$ln(%l)"; }
virtual string emitC() { return "log(%li)"; }
virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return false;}
virtual bool sizeMattersLhs() {return false;}
virtual int instrCount() const { return instrCountDoubleTrig(); }
virtual bool doubleFlavor() const { return true; }
};
class AstLog10D : public AstNodeUniop {
class AstLog10D : public AstNodeSystemUniop {
public:
AstLog10D(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
dtypeSetDouble(); }
AstLog10D(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(Log10D)
virtual void numberOperate(V3Number& out, const V3Number& lhs) {
out.setDouble(log10(lhs.toDouble())); }
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(log10(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$log10(%l)"; }
virtual string emitC() { return "log10(%li)"; }
virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return false;}
virtual bool sizeMattersLhs() {return false;}
virtual int instrCount() const { return instrCountDoubleTrig(); }
virtual bool doubleFlavor() const { return true; }
};
class AstSqrtD : public AstNodeUniop {
class AstExpD : public AstNodeSystemUniop {
public:
AstSqrtD(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
dtypeSetDouble(); }
AstExpD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(ExpD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(exp(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$exp(%l)"; }
virtual string emitC() { return "exp(%li)"; }
};
class AstSqrtD : public AstNodeSystemUniop {
public:
AstSqrtD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(SqrtD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) {
out.setDouble(sqrt(lhs.toDouble())); }
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(sqrt(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$sqrt(%l)"; }
virtual string emitC() { return "sqrt(%li)"; }
virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return false;}
virtual bool sizeMattersLhs() {return false;}
virtual int instrCount() const { return instrCountDoubleTrig(); }
virtual bool doubleFlavor() const { return true; }
};
class AstFloorD : public AstNodeSystemUniop {
public:
AstFloorD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(FloorD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(floor(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$floor(%l)"; }
virtual string emitC() { return "floor(%li)"; }
};
class AstCeilD : public AstNodeSystemUniop {
public:
AstCeilD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(CeilD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(ceil(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$ceil(%l)"; }
virtual string emitC() { return "ceil(%li)"; }
};
class AstSinD : public AstNodeSystemUniop {
public:
AstSinD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(SinD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(sin(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$sin(%l)"; }
virtual string emitC() { return "sin(%li)"; }
};
class AstCosD : public AstNodeSystemUniop {
public:
AstCosD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(CosD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(cos(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$cos(%l)"; }
virtual string emitC() { return "cos(%li)"; }
};
class AstTanD : public AstNodeSystemUniop {
public:
AstTanD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(TanD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(tan(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$tan(%l)"; }
virtual string emitC() { return "tan(%li)"; }
};
class AstAsinD : public AstNodeSystemUniop {
public:
AstAsinD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(AsinD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(asin(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$asin(%l)"; }
virtual string emitC() { return "asin(%li)"; }
};
class AstAcosD : public AstNodeSystemUniop {
public:
AstAcosD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(AcosD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(acos(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$acos(%l)"; }
virtual string emitC() { return "acos(%li)"; }
};
class AstAtanD : public AstNodeSystemUniop {
public:
AstAtanD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(AtanD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(atan(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$atan(%l)"; }
virtual string emitC() { return "atan(%li)"; }
};
class AstSinhD : public AstNodeSystemUniop {
public:
AstSinhD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(SinhD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(sinh(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$sinh(%l)"; }
virtual string emitC() { return "sinh(%li)"; }
};
class AstCoshD : public AstNodeSystemUniop {
public:
AstCoshD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(CoshD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(cosh(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$cosh(%l)"; }
virtual string emitC() { return "cosh(%li)"; }
};
class AstTanhD : public AstNodeSystemUniop {
public:
AstTanhD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(TanhD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(tanh(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$tanh(%l)"; }
virtual string emitC() { return "tanh(%li)"; }
};
class AstAsinhD : public AstNodeSystemUniop {
public:
AstAsinhD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(AsinhD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(asinh(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$asinh(%l)"; }
virtual string emitC() { return "asinh(%li)"; }
};
class AstAcoshD : public AstNodeSystemUniop {
public:
AstAcoshD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(AcoshD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(acosh(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$acosh(%l)"; }
virtual string emitC() { return "acosh(%li)"; }
};
class AstAtanhD : public AstNodeSystemUniop {
public:
AstAtanhD(FileLine* fl, AstNode* lhsp) : AstNodeSystemUniop(fl, lhsp) {}
ASTNODE_NODE_FUNCS(AtanhD)
virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.setDouble(atanh(lhs.toDouble())); }
virtual string emitVerilog() { return "%f$atanh(%l)"; }
virtual string emitC() { return "atanh(%li)"; }
};
//======================================================================
@ -5004,6 +5085,39 @@ public:
AstNode* filep() const { return rhsp(); }
};
class AstNodeSystemBiop : public AstNodeBiop {
public:
AstNodeSystemBiop(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
dtypeSetDouble(); }
virtual bool cleanOut() {return false;}
virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
virtual int instrCount() const { return instrCountDoubleTrig(); }
virtual bool doubleFlavor() const { return true; }
};
class AstAtan2D : public AstNodeSystemBiop {
public:
AstAtan2D(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeSystemBiop(fl, lhsp, rhsp) {}
ASTNODE_NODE_FUNCS(Atan2D)
virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) { return new AstAtan2D(this->fileline(), lhsp, rhsp); }
virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) {
out.setDouble(atan2(lhs.toDouble(), rhs.toDouble())); }
virtual string emitVerilog() { return "%f$atan2(%l,%r)"; }
virtual string emitC() { return "atan2(%li,%ri)"; }
};
class AstHypotD : public AstNodeSystemBiop {
public:
AstHypotD(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeSystemBiop(fl, lhsp, rhsp) {}
ASTNODE_NODE_FUNCS(HypotD)
virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) { return new AstHypotD(this->fileline(), lhsp, rhsp); }
virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) {
out.setDouble(hypot(lhs.toDouble(), rhs.toDouble())); }
virtual string emitVerilog() { return "%f$hypot(%l,%r)"; }
virtual string emitC() { return "hypot(%li,%ri)"; }
};
class AstPattern : public AstNodeMath {
// Verilog '{a,b,c,d...}
// Parents: AstNodeAssign, AstPattern, ...

3
src/V3CCtors.cpp
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@ -77,7 +77,8 @@ public:
m_numStmts += 1;
}
V3CCtorsVisitor(AstNodeModule* nodep, string basename, string argsp="", string callargsp="",
V3CCtorsVisitor(AstNodeModule* nodep, const string& basename,
const string& argsp="", const string& callargsp="",
const string& stmt="") {
m_basename = basename;
m_argsp = argsp;

2
src/V3Config.cpp
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@ -144,7 +144,7 @@ V3ConfigIgnores V3ConfigIgnores::s_singleton;
//######################################################################
// V3Config
void V3Config::addIgnore(V3ErrorCode code, bool on, string filename, int min, int max) {
void V3Config::addIgnore(V3ErrorCode code, bool on, const string& filename, int min, int max) {
if (filename=="*") {
FileLine::globalWarnOff(code,!on);
} else {

2
src/V3Config.h
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@ -30,7 +30,7 @@
class V3Config {
public:
static void addIgnore(V3ErrorCode code, bool on, string filename, int min, int max);
static void addIgnore(V3ErrorCode code, bool on, const string& filename, int min, int max);
static void applyIgnores(FileLine* filelinep);
};

1
src/V3EmitC.cpp
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@ -980,7 +980,6 @@ class EmitCImp : EmitCStmts {
void emitStaticDecl(AstNodeModule* modp);
void emitWrapEval(AstNodeModule* modp);
void emitInt(AstNodeModule* modp);
void writeMakefile(string filename);
public:
EmitCImp() {

5
src/V3GraphDfa.cpp
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@ -69,7 +69,12 @@ private:
// MEMBERS
uint32_t m_step; // Processing step, so we can avoid clearUser all the time
HashMap m_hashMap; // Dfa Vertex for each set of NFA vertexes
#ifdef VL_CPPCHECK
static int debug() { return 9; }
#else
static int debug() { return 0; }
#endif
// METHODS
DfaGraph* graphp() { return static_cast<DfaGraph*>(m_graphp); }

8
src/V3LinkDot.cpp
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@ -604,7 +604,7 @@ class LinkDotFindVisitor : public AstNVisitor {
// METHODS
int debug() { return LinkDotState::debug(); }
virtual AstConst* parseParamLiteral(FileLine* fl, string literal) {
virtual AstConst* parseParamLiteral(FileLine* fl, const string& literal) {
bool success = false;
if (literal[0] == '"') {
// This is a string
@ -2110,10 +2110,8 @@ private:
}
dotSymp = m_statep->findDotted(dotSymp, nodep->dotted(), baddot, okSymp); // Maybe NULL
}
VSymEnt* foundp = NULL;
AstNodeFTask* taskp = NULL;
foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot);
taskp = foundp ? VN_CAST(foundp->nodep(), NodeFTask) : NULL; // Maybe NULL
VSymEnt* foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot);
AstNodeFTask* taskp = foundp ? VN_CAST(foundp->nodep(), NodeFTask) : NULL; // Maybe NULL
if (taskp) {
nodep->taskp(taskp);
nodep->packagep(foundp->packagep());

1
src/V3Localize.cpp
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@ -66,6 +66,7 @@ protected:
int m_stdFuncAsn:1; // Found simple assignment
int m_done:1; // Removed
};
// cppcheck-suppress unusedStructMember
uint32_t m_flags;
VarFlags(AstNode* nodep) { m_flags = nodep->user2(); }
void setNodeFlags(AstNode* nodep) { nodep->user2(m_flags); }

6
src/V3Options.cpp
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@ -155,11 +155,11 @@ void V3Options::addParameter(const string& paramline, bool allowPlus) {
}
}
bool V3Options::hasParameter(string name) {
bool V3Options::hasParameter(const string& name) {
return m_parameters.find(name) != m_parameters.end();
}
string V3Options::parameter(string name) {
string V3Options::parameter(const string& name) {
string value = m_parameters.find(name)->second;
m_parameters.erase(m_parameters.find(name));
return value;
@ -1284,7 +1284,7 @@ V3Options::V3Options() {
VName::maxLength(128); // Linux filename limits 256; leave half for prefix
optimize(true);
optimize(1);
// Default +libext+
addLibExtV(""); // So include "filename.v" will find the same file
addLibExtV(".v");

4
src/V3Options.h
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@ -293,8 +293,8 @@ class V3Options {
const V3StringList& forceIncs() const { return m_forceIncs; }
const V3LangCode& defaultLanguage() const { return m_defaultLanguage; }
bool hasParameter(string name);
string parameter(string name);
bool hasParameter(const string& name);
string parameter(const string& name);
void checkParameters();
bool isFuture(const string& flag) const;

2
src/V3String.cpp
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@ -205,7 +205,7 @@ string VHashSha1::digestBinary() {
finalize();
string out; out.reserve(20);
for (size_t i=0; i<20; ++i) {
out[i] = (m_inthash[i >> 2] >> (((3 - i) & 0x3) << 3)) & 0xff;
out += (m_inthash[i >> 2] >> (((3 - i) & 0x3) << 3)) & 0xff;
}
return out;
}

2
src/V3Task.cpp
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@ -795,7 +795,7 @@ private:
makePortList(nodep, rtnvarp, dpip);
}
bool duplicatedDpiProto(AstNodeFTask* nodep, string dpiproto) {
bool duplicatedDpiProto(AstNodeFTask* nodep, const string& dpiproto) {
// Only create one DPI extern prototype for each specified cname
// as it's legal for the user to attach multiple tasks to one dpi cname
DpiNames::iterator iter = m_dpiNames.find(nodep->cname());

57
src/V3Tristate.cpp
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@ -984,32 +984,37 @@ class TristateVisitor : public TristateBaseVisitor {
virtual void visit(AstPull* nodep) {
UINFO(9,dbgState()<<nodep<<endl);
if (m_graphing) {
if (AstVarRef* lhsp = VN_CAST(nodep->lhsp(), VarRef)) {
lhsp->lvalue(true);
m_logicp = nodep;
m_tgraph.setTristate(nodep);
associateLogic(nodep, lhsp->varp());
m_logicp = NULL;
} else {
nodep->v3error("Unsupported pullup/down (weak driver) construct.");
}
} else {
// Replace any pullup/pulldowns with assignw logic and set the
// direction of the pull in the user3() data on the var. Given
// the complexity of merging tristate drivers at any level, the
// current limitation of this implementation is that a pullup/down
// gets applied to all bits of a bus and a bus cannot have drivers
// in opposite directions on indvidual pins.
if (AstVarRef* lhsp = VN_CAST(nodep->lhsp(), VarRef)) {
lhsp->lvalue(true);
m_tgraph.didProcess(nodep);
m_tgraph.didProcess(lhsp->varp());
AstVar* varp = lhsp->varp();
setPullDirection(varp, nodep);
} else {
nodep->v3error("Unsupported pullup/down (weak driver) construct.");
}
AstVarRef* varrefp = NULL;
if (VN_IS(nodep->lhsp(), VarRef)) {
varrefp = VN_CAST(nodep->lhsp(), VarRef);
} else if (VN_IS(nodep->lhsp(), Sel)
&& VN_IS(VN_CAST(nodep->lhsp(), Sel)->fromp(), VarRef)) {
varrefp = VN_CAST(VN_CAST(nodep->lhsp(), Sel)->fromp(), VarRef);
}
if (!varrefp) {
if (debug()>=4) nodep->dumpTree(cout, "- ");
nodep->v3error("Unsupported pullup/down (weak driver) construct.");
} else {
if (m_graphing) {
varrefp->lvalue(true);
m_logicp = nodep;
m_tgraph.setTristate(nodep);
associateLogic(nodep, varrefp->varp());
m_logicp = NULL;
} else {
// Replace any pullup/pulldowns with assignw logic and set the
// direction of the pull in the user3() data on the var. Given
// the complexity of merging tristate drivers at any level, the
// current limitation of this implementation is that a pullup/down
// gets applied to all bits of a bus and a bus cannot have drivers
// in opposite directions on indvidual pins.
varrefp->lvalue(true);
m_tgraph.didProcess(nodep);
m_tgraph.didProcess(varrefp->varp());
setPullDirection(varrefp->varp(), nodep);
}
}
if (!m_graphing) {
nodep->unlinkFrBack();
pushDeletep(nodep); VL_DANGLING(nodep); // Node must persist as user3p points to it
}

4
src/V3Unroll.cpp
View File

@ -455,7 +455,7 @@ private:
public:
// CONSTUCTORS
UnrollVisitor(AstNode* nodep, bool generate, string beginName) {
UnrollVisitor(AstNode* nodep, bool generate, const string& beginName) {
m_forVarp = NULL;
m_forVscp = NULL;
m_ignoreIncp = NULL;
@ -481,7 +481,7 @@ void V3Unroll::unrollAll(AstNetlist* nodep) {
V3Global::dumpCheckGlobalTree("unroll", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3);
}
void V3Unroll::unrollGen(AstNodeFor* nodep, string beginName) {
void V3Unroll::unrollGen(AstNodeFor* nodep, const string& beginName) {
UINFO(2,__FUNCTION__<<": "<<endl);
UnrollVisitor visitor (nodep, true, beginName);
}

2
src/V3Unroll.h
View File

@ -30,7 +30,7 @@
class V3Unroll {
public:
static void unrollAll(AstNetlist* nodep);
static void unrollGen(AstNodeFor* nodep, string beginName);
static void unrollGen(AstNodeFor* nodep, const string& beginName);
};
#endif // Guard

18
src/V3Width.cpp
View File

@ -299,14 +299,10 @@ private:
virtual void visit(AstDivD* nodep) { visit_real_add_sub(nodep); }
virtual void visit(AstMulD* nodep) { visit_real_add_sub(nodep); }
virtual void visit(AstPowD* nodep) { visit_real_add_sub(nodep); }
virtual void visit(AstNodeSystemBiop* nodep) { visit_real_add_sub(nodep); }
// Real: Output real
virtual void visit(AstNegateD* nodep) { visit_real_neg_ceil(nodep); }
virtual void visit(AstCeilD* nodep) { visit_real_neg_ceil(nodep); }
virtual void visit(AstExpD* nodep) { visit_real_neg_ceil(nodep); }
virtual void visit(AstFloorD* nodep) { visit_real_neg_ceil(nodep); }
virtual void visit(AstLogD* nodep) { visit_real_neg_ceil(nodep); }
virtual void visit(AstLog10D* nodep) { visit_real_neg_ceil(nodep); }
virtual void visit(AstSqrtD* nodep) { visit_real_neg_ceil(nodep); }
virtual void visit(AstNodeSystemUniop* nodep) { visit_real_neg_ceil(nodep); }
// Widths: out signed/unsigned width = lhs width, input un|signed
virtual void visit(AstSigned* nodep) { visit_signed_unsigned(nodep, AstNumeric::SIGNED); }
@ -556,6 +552,7 @@ private:
// LSB is self-determined (IEEE 2012 11.5.1)
// We also use SELs to shorten a signed constant etc, in this case they are signed.
if (nodep->didWidth()) return;
if (!m_vup) nodep->v3fatalSrc("Select under an unexpected context");
if (m_vup->prelim()) {
if (debug()>=9) nodep->dumpTree(cout,"-selWidth: ");
userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT,PRELIM).p());
@ -950,6 +947,10 @@ private:
}
m_attrp = oldAttr;
}
virtual void visit(AstPull* nodep) {
// May have select underneath, let seek natural size
userIterateChildren(nodep, WidthVP(SELF,BOTH).p());
}
virtual void visit(AstText* nodep) {
// Only used in CStmts which don't care....
}
@ -3157,8 +3158,7 @@ private:
} else {
bool bad = widthBad(underp,nodep->findLogicBoolDType());
if (bad) {
bool warnOn = true; // Not used
if (warnOn) {
{ // if (warnOn), but not needed here
if (debug()>4) nodep->backp()->dumpTree(cout," back: ");
nodep->v3warn(WIDTH,"Logical Operator "<<nodep->prettyTypeName()
<<" expects 1 bit on the "<<side<<", but "<<side<<"'s "
@ -3655,7 +3655,7 @@ private:
// Find valid values and populate
if (!nodep->itemsp()) nodep->v3fatalSrc("enum without items");
std::vector<AstNode*> values;
values.reserve(msbdim+1);
values.resize(msbdim+1);
for (unsigned i=0; i<(msbdim+1); ++i) {
values[i] = NULL;
}

2
src/flexfix
View File

@ -18,6 +18,8 @@
my $Opt_Prefix = $ARGV[0] or die "%Error: No prefix specified,";
foreach my $line (<STDIN>) {
# Fix flex 2.6.1 warning
$line =~ s/for \( i = 0; i < _yybytes_len; \+\+i \)/for ( i = 0; i < (yy_size_t)(_yybytes_len); ++i )/g;
# Fix flex 2.6.0 warning
$line =~ s/\(\(int\) \(\(yy_n_chars\) \+ number_to_move\) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size\)/((int) ((yy_n_chars) + number_to_move) > (int) YY_CURRENT_BUFFER_LVALUE->yy_buf_size)/g;
$line =~ s/ number_to_move == YY_MORE_ADJ / (int)number_to_move == (int)YY_MORE_ADJ /;

38
src/verilog.l
View File

@ -206,8 +206,17 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Extensions to Verilog set, some specified by PSL */
"$c"[0-9]* { FL; return yD_C; } /*Verilator only*/
/* System Tasks */
"$acos" { FL; return yD_ACOS; }
"$acosh" { FL; return yD_ACOSH; }
"$asin" { FL; return yD_ASIN; }
"$asinh" { FL; return yD_ASINH; }
"$atan" { FL; return yD_ATAN; }
"$atan2" { FL; return yD_ATAN2; }
"$atanh" { FL; return yD_ATANH; }
"$bitstoreal" { FL; return yD_BITSTOREAL; }
"$ceil" { FL; return yD_CEIL; }
"$cos" { FL; return yD_COS; }
"$cosh" { FL; return yD_COSH; }
"$display" { FL; return yD_DISPLAY; }
"$exp" { FL; return yD_EXP; }
"$fclose" { FL; return yD_FCLOSE; }
@ -223,6 +232,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"$fullskew" { FL; return yaTIMINGSPEC; }
"$fwrite" { FL; return yD_FWRITE; }
"$hold" { FL; return yaTIMINGSPEC; }
"$hypot" { FL; return yD_HYPOT; }
"$itor" { FL; return yD_ITOR; }
"$ln" { FL; return yD_LN; }
"$log10" { FL; return yD_LOG10; }
@ -242,6 +252,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"$setuphold" { FL; return yaTIMINGSPEC; }
"$sformat" { FL; return yD_SFORMAT; }
"$sformatf" { FL; return yD_SFORMATF; }
"$sin" { FL; return yD_SIN; }
"$sinh" { FL; return yD_SINH; }
"$skew" { FL; return yaTIMINGSPEC; }
"$sqrt" { FL; return yD_SQRT; }
"$sscanf" { FL; return yD_SSCANF; }
@ -249,6 +261,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"$stop" { FL; return yD_STOP; }
"$swrite" { FL; return yD_SWRITE; }
"$system" { FL; return yD_SYSTEM; }
"$tan" { FL; return yD_TAN; }
"$tanh" { FL; return yD_TANH; }
"$test$plusargs" { FL; return yD_TESTPLUSARGS; }
"$time" { FL; return yD_TIME; }
"$timeskew" { FL; return yaTIMINGSPEC; }
@ -601,20 +615,20 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"aliasparam" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"analog" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"analysis" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"asin" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"asinh" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"asin" { FL; return yD_ASIN; }
"asinh" { FL; return yD_ASINH; }
"assert" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"atan" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"atan2" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"atanh" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"atan" { FL; return yD_ATAN; }
"atan2" { FL; return yD_ATAN2; }
"atanh" { FL; return yD_ATANH; }
"branch" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"ceil" { FL; return yD_CEIL; }
"connect" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"connectmodule" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"connectrules" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"continuous" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"cos" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"cosh" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"cos" { FL; return yD_COS; }
"cosh" { FL; return yD_COSH; }
"cross" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"ddt" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"ddt_nature" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
@ -635,7 +649,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"flow" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"from" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"ground" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"hypot" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"hypot" { FL; return yD_HYPOT; }
"idt" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"idt_nature" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"idtmod" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
@ -659,14 +673,14 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"potential" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"pow" { FL; return yD_POW; }
"resolveto" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"sin" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"sinh" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"sin" { FL; return yD_SIN; }
"sinh" { FL; return yD_SINH; }
"slew" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"split" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"sqrt" { FL; return yD_SQRT; }
"string" { FL; return ySTRING; }
"tan" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"tanh" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"tan" { FL; return yD_TAN; }
"tanh" { FL; return yD_TANH; }
"timer" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"transition" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"units" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }

28
src/verilog.y
View File

@ -442,11 +442,20 @@ class AstSenTree;
%token<fl> yXNOR "xnor"
%token<fl> yXOR "xor"
%token<fl> yD_ACOS "$acos"
%token<fl> yD_ACOSH "$acosh"
%token<fl> yD_ASIN "$asin"
%token<fl> yD_ASINH "$asinh"
%token<fl> yD_ATAN "$atan"
%token<fl> yD_ATAN2 "$atan2"
%token<fl> yD_ATANH "$atanh"
%token<fl> yD_BITS "$bits"
%token<fl> yD_BITSTOREAL "$bitstoreal"
%token<fl> yD_C "$c"
%token<fl> yD_CEIL "$ceil"
%token<fl> yD_CLOG2 "$clog2"
%token<fl> yD_COS "$cos"
%token<fl> yD_COSH "$cosh"
%token<fl> yD_COUNTONES "$countones"
%token<fl> yD_DIMENSIONS "$dimensions"
%token<fl> yD_DISPLAY "$display"
@ -465,6 +474,7 @@ class AstSenTree;
%token<fl> yD_FSCANF "$fscanf"
%token<fl> yD_FWRITE "$fwrite"
%token<fl> yD_HIGH "$high"
%token<fl> yD_HYPOT "$hypot"
%token<fl> yD_INCREMENT "$increment"
%token<fl> yD_INFO "$info"
%token<fl> yD_ISUNKNOWN "$isunknown"
@ -486,6 +496,8 @@ class AstSenTree;
%token<fl> yD_SFORMAT "$sformat"
%token<fl> yD_SFORMATF "$sformatf"
%token<fl> yD_SIGNED "$signed"
%token<fl> yD_SIN "$sin"
%token<fl> yD_SINH "$sinh"
%token<fl> yD_SIZE "$size"
%token<fl> yD_SQRT "$sqrt"
%token<fl> yD_SSCANF "$sscanf"
@ -493,6 +505,8 @@ class AstSenTree;
%token<fl> yD_STOP "$stop"
%token<fl> yD_SWRITE "$swrite"
%token<fl> yD_SYSTEM "$system"
%token<fl> yD_TAN "$tan"
%token<fl> yD_TANH "$tanh"
%token<fl> yD_TESTPLUSARGS "$test$plusargs"
%token<fl> yD_TIME "$time"
%token<fl> yD_UNIT "$unit"
@ -2693,12 +2707,21 @@ system_f_call<nodep>: // IEEE: system_tf_call (as func)
| yaD_DPI parenE { $$ = new AstFuncRef($<fl>1,*$1,NULL); }
| yaD_DPI '(' exprList ')' { $$ = new AstFuncRef($2,*$1,$3); GRAMMARP->argWrapList(VN_CAST($$, FuncRef)); }
//
| yD_ACOS '(' expr ')' { $$ = new AstAcosD($1,$3); }
| yD_ACOSH '(' expr ')' { $$ = new AstAcoshD($1,$3); }
| yD_ASIN '(' expr ')' { $$ = new AstAsinD($1,$3); }
| yD_ASINH '(' expr ')' { $$ = new AstAsinhD($1,$3); }
| yD_ATAN '(' expr ')' { $$ = new AstAtanD($1,$3); }
| yD_ATAN2 '(' expr ',' expr ')' { $$ = new AstAtan2D($1,$3,$5); }
| yD_ATANH '(' expr ')' { $$ = new AstAtanhD($1,$3); }
| yD_BITS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_BITS,$3); }
| yD_BITS '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_BITS,$3,$5); }
| yD_BITSTOREAL '(' expr ')' { $$ = new AstBitsToRealD($1,$3); }
| yD_C '(' cStrList ')' { $$ = (v3Global.opt.ignc() ? NULL : new AstUCFunc($1,$3)); }
| yD_CEIL '(' expr ')' { $$ = new AstCeilD($1,$3); }
| yD_CLOG2 '(' expr ')' { $$ = new AstCLog2($1,$3); }
| yD_COS '(' expr ')' { $$ = new AstCosD($1,$3); }
| yD_COSH '(' expr ')' { $$ = new AstCoshD($1,$3); }
| yD_COUNTONES '(' expr ')' { $$ = new AstCountOnes($1,$3); }
| yD_DIMENSIONS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_DIMENSIONS,$3); }
| yD_EXP '(' expr ')' { $$ = new AstExpD($1,$3); }
@ -2709,6 +2732,7 @@ system_f_call<nodep>: // IEEE: system_tf_call (as func)
| yD_FSCANF '(' expr ',' str commaVRDListE ')' { $$ = new AstFScanF($1,*$5,$3,$6); }
| yD_HIGH '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_HIGH,$3,NULL); }
| yD_HIGH '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_HIGH,$3,$5); }
| yD_HYPOT '(' expr ',' expr ')' { $$ = new AstHypotD($1,$3,$5); }
| yD_INCREMENT '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_INCREMENT,$3,NULL); }
| yD_INCREMENT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_INCREMENT,$3,$5); }
| yD_ISUNKNOWN '(' expr ')' { $$ = new AstIsUnknown($1,$3); }
@ -2731,12 +2755,16 @@ system_f_call<nodep>: // IEEE: system_tf_call (as func)
| yD_RTOI '(' expr ')' { $$ = new AstRToIS($1,$3); }
| yD_SFORMATF '(' str commaEListE ')' { $$ = new AstSFormatF($1,*$3,false,$4); }
| yD_SIGNED '(' expr ')' { $$ = new AstSigned($1,$3); }
| yD_SIN '(' expr ')' { $$ = new AstSinD($1,$3); }
| yD_SINH '(' expr ')' { $$ = new AstSinhD($1,$3); }
| yD_SIZE '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_SIZE,$3,NULL); }
| yD_SIZE '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_SIZE,$3,$5); }
| yD_SQRT '(' expr ')' { $$ = new AstSqrtD($1,$3); }
| yD_SSCANF '(' expr ',' str commaVRDListE ')' { $$ = new AstSScanF($1,*$5,$3,$6); }
| yD_STIME parenE { $$ = new AstSel($1,new AstTime($1),0,32); }
| yD_SYSTEM '(' expr ')' { $$ = new AstSystemF($1,$3); }
| yD_TAN '(' expr ')' { $$ = new AstTanD($1,$3); }
| yD_TANH '(' expr ')' { $$ = new AstTanhD($1,$3); }
| yD_TESTPLUSARGS '(' str ')' { $$ = new AstTestPlusArgs($1,*$3); }
| yD_TIME parenE { $$ = new AstTime($1); }
| yD_UNPACKED_DIMENSIONS '(' exprOrDataType ')' { $$ = new AstAttrOf($1,AstAttrType::DIM_UNPK_DIMENSIONS,$3); }

11
test_regress/t/t_math_trig.v
View File

@ -16,7 +16,7 @@ module t (/*AUTOARG*/
task check(integer line, real got, real ex);
if (got != ex) begin
if ((got - ex) > 0.000001) begin
if ((got > ex ? got - ex : ex - got) > 0.000001) begin
$display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex);
$stop;
end
@ -45,7 +45,6 @@ module t (/*AUTOARG*/
check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125);
//check(`__LINE__, $sqrt(-1.2), 0); // Bad value
check(`__LINE__, ((1.5)**(1.25)), 1.660023);
`ifndef VERILATOR
check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1
check(`__LINE__, $acosh(1.2), 0.622362503);
check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1
@ -60,7 +59,6 @@ module t (/*AUTOARG*/
check(`__LINE__, $sinh (1.2), 1.509461355);
check(`__LINE__, $tan (1.2), 2.572151622);
check(`__LINE__, $tanh (1.2), 0.833654607);
`endif
end
real sum_ceil;
@ -108,7 +106,6 @@ module t (/*AUTOARG*/
if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3);
if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r);
`ifndef VERILATOR
if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r);
if (r>=1.0) sum_acosh += 1.0+$acosh(r);
if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r);
@ -123,7 +120,6 @@ module t (/*AUTOARG*/
sum_sinh += 1.0+$sinh (r);
sum_tan += 1.0+$tan (r);
sum_tanh += 1.0+$tanh (r);
`endif
end
else if (cyc==99) begin
check (`__LINE__, sum_ceil, 85);
@ -134,7 +130,6 @@ module t (/*AUTOARG*/
check (`__LINE__, sum_pow1, 410.98798177);
check (`__LINE__, sum_pow2, 321.94765689);
check (`__LINE__, sum_sqrt, 92.269677253);
`ifndef VERILATOR
check (`__LINE__, sum_acos, 53.986722862);
check (`__LINE__, sum_acosh, 72.685208498);
check (`__LINE__, sum_asin, 21);
@ -146,10 +141,10 @@ module t (/*AUTOARG*/
check (`__LINE__, sum_cosh, 1054.0178222);
check (`__LINE__, sum_hypot, 388.92858406);
check (`__LINE__, sum_sin, 98.264184989);
check (`__LINE__, sum_sinh, 0);
check (`__LINE__, sum_sinh, -356.9512927);
check (`__LINE__, sum_tan, 1.7007946043);
check (`__LINE__, sum_tanh, 79.003199681);
`endif
$write("*-* All Finished *-*\n");
$finish;
end

18
test_regress/t/t_tri_array_pull.pl Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

43
test_regress/t/t_tri_array_pull.v Normal file
View File

@ -0,0 +1,43 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Rod Steward.
module IOBUF ( input T, input I, output O, inout IO );
assign O = IO;
assign IO = T ? 1'bz : I;
endmodule
module t
(
input [7:0] inlines,
output [7:0] outlines,
inout [7:0] iolines,
input inctrl
);
generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D
IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) );
pullup d_pup (iolines[i]);
end
endgenerate
IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) );
pullup d_0_pup (iolines[0]);
IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) );
pullup d_1_pup (iolines[1]);
IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) );
pullup d_2_pup (iolines[2]);
IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) );
pullup d_3_pup (iolines[3]);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

23
test_regress/t/t_tri_pullvec_bad.pl Executable file
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@ -0,0 +1,23 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
$Self->{vlt} or $Self->skip("Verilator only test");
compile (
v_flags2 => ["--lint-only"],
fails=>$Self->{v3},
expect=>
'%Error: t/t_tri_pullvec_bad.v:\d+: Unsupported: Conflicting pull directions.
%Error: t/t_tri_pullvec_bad.v:\d+: ... Location of conflicting pull.
%Error: t/t_tri_pullvec_bad.v:\d+: Unsupported: Conflicting pull directions.
%Error: Exiting due to .*'
);
ok(1);
1;

19
test_regress/t/t_tri_pullvec_bad.v Normal file
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@ -0,0 +1,19 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder
module t (clk);
input clk;
tri [3:0] w;
pullup p0 (w[0]);
pulldown p1 (w[1]);
pulldown p2 (w[2]);
pullup p3 (w[3]);
always_ff @ (posedge clk) begin
if (w != 4'b1001) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

14
test_regress/t/t_verilated_all_oldest.pl
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@ -7,19 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
top_filename("t/t_verilated_all.v");
my $root = "..";
compile (
# Can't use --coverage and --savable together, so cheat and compile inline
verilator_flags2 => ['--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi $root/include/verilated_save.cpp'],
make_flags => 'DRIVER_STD=oldest',
);
execute (
check_finished=>1,
);
# This test now does nothing, because using DRIVER_STD=oldest tends to blow up glibc.
ok(1);
1;