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For --xml, add additional var information, bug1372.

This commit is contained in:
Wilson Snyder 2018-12-06 07:12:39 -05:00
parent a226111829
commit ede7236945
5 changed files with 29 additions and 15 deletions
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2
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@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 4.009 devel * Verilator 4.009 devel
**** For --xml, add additional var information, bug1372. [Jonathan Kimmitt]
* Verilator 4.008 2018-12-01 * Verilator 4.008 2018-12-01

2
src/V3AstNodes.cpp
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@ -200,6 +200,8 @@ string AstVar::verilogKwd() const {
return "wire"; return "wire";
} else if (varType()==AstVarType::WREAL) { } else if (varType()==AstVarType::WREAL) {
return "wreal"; return "wreal";
} else if (varType()==AstVarType::IFACEREF) {
return "ifaceref";
} else { } else {
return dtypep()->name(); return dtypep()->name();
} }

10
src/V3EmitXml.cpp
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@ -115,7 +115,17 @@ class EmitXmlFileVisitor : public AstNVisitor {
outputChildrenEnd(nodep, ""); outputChildrenEnd(nodep, "");
} }
virtual void visit(AstVar* nodep) { virtual void visit(AstVar* nodep) {
AstVarType typ = nodep->varType();
string kw = nodep->verilogKwd();
string vt = nodep->dtypep()->name();
outputTag(nodep, ""); outputTag(nodep, "");
if (nodep->isIO()) {
puts(" dir="); putsQuoted(kw);
puts(" vartype="); putsQuoted(!vt.empty()
? vt : typ == AstVarType::PORT ? "port" : "unknown");
} else {
puts(" vartype="); putsQuoted(!vt.empty() ? vt : kw);
}
puts(" origName="); putsQuoted(nodep->origName()); puts(" origName="); putsQuoted(nodep->origName());
outputChildrenEnd(nodep, ""); outputChildrenEnd(nodep, "");
} }

20
test_regress/t/t_xml_first.out
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@ -20,10 +20,10 @@
</cells> </cells>
<netlist> <netlist>
<module fl="f6" name="t" origName="t" topModule="1"> <module fl="f6" name="t" origName="t" topModule="1">
<var fl="f12" name="clk" dtype_id="1" origName="clk"/> <var fl="f12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="f13" name="d" dtype_id="2" origName="d"/> <var fl="f13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="f14" name="q" dtype_id="2" origName="q"/> <var fl="f14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<var fl="f16" name="between" dtype_id="2" origName="between"/> <var fl="f16" name="between" dtype_id="2" vartype="logic" origName="between"/>
<instance fl="f18" name="cell1" defName="mod1" origName="cell1"> <instance fl="f18" name="cell1" defName="mod1" origName="cell1">
<port fl="f18" name="q" direction="out" portIndex="1"> <port fl="f18" name="q" direction="out" portIndex="1">
<varref fl="f18" name="between" dtype_id="2"/> <varref fl="f18" name="between" dtype_id="2"/>
@ -48,9 +48,9 @@
</instance> </instance>
</module> </module>
<module fl="f33" name="mod1" origName="mod1"> <module fl="f33" name="mod1" origName="mod1">
<var fl="f35" name="clk" dtype_id="1" origName="clk"/> <var fl="f35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="f36" name="d" dtype_id="2" origName="d"/> <var fl="f36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="f37" name="q" dtype_id="2" origName="q"/> <var fl="f37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<always fl="f39"> <always fl="f39">
<sentree fl="f39"> <sentree fl="f39">
<senitem fl="f39" edgeType="POS"> <senitem fl="f39" edgeType="POS">
@ -64,9 +64,9 @@
</always> </always>
</module> </module>
<module fl="f44" name="mod2" origName="mod2"> <module fl="f44" name="mod2" origName="mod2">
<var fl="f46" name="clk" dtype_id="1" origName="clk"/> <var fl="f46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="f47" name="d" dtype_id="2" origName="d"/> <var fl="f47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="f48" name="q" dtype_id="2" origName="q"/> <var fl="f48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<contassign fl="f51" dtype_id="2"> <contassign fl="f51" dtype_id="2">
<varref fl="f51" name="d" dtype_id="2"/> <varref fl="f51" name="d" dtype_id="2"/>
<varref fl="f51" name="q" dtype_id="2"/> <varref fl="f51" name="q" dtype_id="2"/>

8
test_regress/t/t_xml_tag.out
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@ -17,11 +17,11 @@
</cells> </cells>
<netlist> <netlist>
<module fl="f6" name="m" origName="m"> <module fl="f6" name="m" origName="m">
<var fl="f8" name="clk_ip" tag="clk_ip" dtype_id="1" origName="clk_ip"/> <var fl="f8" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" vartype="logic" origName="clk_ip"/>
<var fl="f9" name="rst_ip" dtype_id="1" origName="rst_ip"/> <var fl="f9" name="rst_ip" dtype_id="1" dir="input" vartype="logic" origName="rst_ip"/>
<var fl="f10" name="foo_op" tag="foo_op" dtype_id="1" origName="foo_op"/> <var fl="f10" name="foo_op" tag="foo_op" dtype_id="1" dir="output" vartype="logic" origName="foo_op"/>
<typedef fl="f14" name="my_struct" tag="my_struct" dtype_id="2"/> <typedef fl="f14" name="my_struct" tag="my_struct" dtype_id="2"/>
<var fl="f23" name="this_struct" tag="this_struct" dtype_id="3" origName="this_struct"/> <var fl="f23" name="this_struct" tag="this_struct" dtype_id="3" vartype="" origName="this_struct"/>
</module> </module>
<typetable fl="a0"> <typetable fl="a0">
<basicdtype fl="f23" id="4" name="logic" left="31" right="0"/> <basicdtype fl="f23" id="4" name="logic" left="31" right="0"/>