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Allow assigns to create implicit wires 

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1004 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-03-20 01:40:22 +00:00
parent 4a1729eaab
commit ede37bb9d8
5 changed files with 62 additions and 4 deletions
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2
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@ -22,6 +22,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix definitions in main file.v, referenced in library. [Stefan Thiede] **** Fix definitions in main file.v, referenced in library. [Stefan Thiede]
**** Fix undefined assigns to be implicit warnings. [Stefan Thiede]
* Verilator 3.658 2008/02/25 * Verilator 3.658 2008/02/25
**** Fix unistd compile error in 3.657. [Patricio Kaplan, Jonathan Kimmitt] **** Fix unistd compile error in 3.657. [Patricio Kaplan, Jonathan Kimmitt]

8
src/V3Link.cpp
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@ -381,10 +381,10 @@ private:
virtual void visit(AstAssignW* nodep, AstNUser*) { virtual void visit(AstAssignW* nodep, AstNUser*) {
// Deal with implicit definitions // Deal with implicit definitions
if (nodep->allowImplicit()) { // We used to nodep->allowImplicit() here, but it turns out
if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) { // normal "assigns" can also make implicit wires. Yuk.
createImplicitVar(forrefp, false); if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) {
} createImplicitVar(forrefp, false);
} }
nodep->iterateChildren(*this); nodep->iterateChildren(*this);
} }

16
test_regress/t/t_lint_implicit.pl Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["-Wno-IMPLICIT"],
) if $Last_Self->{v3};
ok(1);
1;

16
test_regress/t/t_lint_implicit.v Normal file
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@ -0,0 +1,16 @@
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (a,z);
input a;
output z;
assign b = 1'b1;
or OR0 (nt0, a, b);
assign z = nt0;
endmodule

24
test_regress/t/t_lint_implicit_bad.pl Executable file
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@ -0,0 +1,24 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
top_filename("t/t_lint_implicit.v");
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Warning-IMPLICIT: t/t_lint_implicit.v:\d+: Signal definition not found, creating implicitly: b
%Warning-IMPLICIT: Use .* to disable this message.
%Warning-IMPLICIT: t/t_lint_implicit.v:\d+: Signal definition not found, creating implicitly: nt0
%Error: Exiting due to.*',
) if $Last_Self->{v3};
ok(1);
1;