Tests: Add tests for bug1487.

test_regress/t/t_lint_width_genfor.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug1487.");
+
+scenarios(linter => 1);
+
+lint();
+
+ok(1);
+1;

test_regress/t/t_lint_width_genfor.v

@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   rc, rg, ri, rp
+   );
+
+   parameter P = 15;
+
+   output reg [3:0] rc;
+   output reg [3:0] rg;
+   output reg [3:0] ri;
+   output reg [3:0] rp;
+
+   for (genvar g=0; g < 15; ++g) begin
+      // bug1487
+      // This isn't a width violation, as genvars are generally 32 bits
+      initial begin
+         rg = g;
+         rp = P;
+         rc = 1;
+      end
+   end
+   initial begin
+      for (integer i=0; i < 15; ++i) begin
+         ri = i;
+      end
+   end
+
+endmodule

test_regress/t/t_lint_width_genfor_bad.out

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+%Warning-WIDTH: t/t_lint_width_genfor_bad.v:24: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '32'h10' generates 32 bits.
+                                              : ... In instance t
+         rg = g;   
+            ^
+                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
+%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits.
+                                              : ... In instance t
+         rp = P;   
+            ^
+%Warning-WIDTH: t/t_lint_width_genfor_bad.v:26: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits.
+                                              : ... In instance t
+         rw = w;   
+            ^
+%Warning-WIDTH: t/t_lint_width_genfor_bad.v:27: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
+                                              : ... In instance t
+         rc = 64'h1;   
+            ^
+%Warning-WIDTH: t/t_lint_width_genfor_bad.v:32: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits.
+                                              : ... In instance t
+         ri = i;   
+            ^
+%Error: Exiting due to

test_regress/t/t_lint_width_genfor_bad.pl

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+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_lint_width_genfor_bad.v

@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   rc, rg, ri, rp, rw
+   );
+
+   parameter P = 17;
+   wire [4:0] w = 5'd1;
+
+   output reg [3:0] rc;
+   output reg [3:0] rg;
+   output reg [3:0] ri;
+   output reg [3:0] rp;
+
+   output reg [3:0] rw;
+
+   for (genvar g=16; g < 17; ++g) begin
+      // Index 17 makes a width violation
+      initial begin
+         rg = g;  // WidthMin mismatch
+         rp = P;  // WidthMin mismatch
+         rw = w;  // Always a mismatch
+         rc = 64'h1;  // Always a mismatch (as sized)
+      end
+   end
+   initial begin
+      for (integer i=16; i < 17; ++i) begin
+         ri = i;  // WidthMin mismatch
+      end
+   end
+
+endmodule