Tests: Add t_forceable_public flat (#3955)

test_regress/t/t_forceable_public_flat.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile()
+
+files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h")
+test.file_grep_any(files, r' u_sub__DOT__a__VforceRd')
+test.file_grep_any(files, r' u_sub__DOT__a__VforceEn')
+test.file_grep_any(files, r' u_sub__DOT__a__VforceVal')
+
+test.passes()

test_regress/t/t_forceable_public_flat.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+    input x,
+    input y,
+    output z
+);
+
+  logic t2  /* verilator public */;
+  logic t3;
+
+  sub u_sub (
+      x,
+      y,
+      t3
+  );
+
+  assign t2 = t3 | x;
+  assign z = t2;
+
+endmodule
+
+module sub (
+    input a  /* verilator forceable */ /* verilator public_flat */,
+    input b,
+    output c
+);
+
+  logic t1;
+
+  assign t1 = a & b;
+  assign c = t1;
+
+endmodule