CR -> CRC

test_regress/t/t_assert_nexttime.v

@@ -4,24 +4,56 @@
 // SPDX-FileCopyrightText: 2026 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
-   input clk;
-   int cyc = 0;
+module t (
+    input clk
+);
+  integer cyc = 0;
+  reg [63:0] crc = '0;
+  reg [63:0] sum = '0;
 
-   always @(posedge clk) begin
-      cyc <= cyc + 1;
-   end
+  // Derive test signals from CRC
+  wire a = crc[0];
+  wire b = crc[1];
+  wire c = crc[2];
+  wire d = crc[3];
 
-   assert property (@(posedge clk) nexttime (cyc > 0));
+  // Aggregate outputs into a single result vector
+  wire [63:0] result = {60'h0, d, c, b, a};
+
+  always_ff @(posedge clk) begin
+`ifdef TEST_VERBOSE
+    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
+           $time, cyc, crc, a, b, c, d);
+`endif
+    cyc <= cyc + 1;
+    crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+    sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
+
+    if (cyc == 0) begin
+      crc <= 64'h5aef0c8d_d70a4497;
+      sum <= '0;
+    end else if (cyc < 10) begin
+      sum <= '0;
+    end else if (cyc == 99) begin
+      `checkh(crc, 64'hc77bb9b3784ea091)
+      `checkh(sum, 64'hdb7bc8bfe61f987e)
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+
+  // =========================================================================
+  // nexttime: property must hold at the next clock tick
+  // =========================================================================
+
+  assert property (@(posedge clk) nexttime (1'b1));
+  assert property (@(posedge clk) nexttime (cyc > 0));
+  assert property (@(posedge clk) disable iff (b) nexttime ~c);
+  assert property (@(posedge clk) disable iff (~b) nexttime c);
 
-   always @(posedge clk) begin
-      if (cyc == 20) begin
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
 endmodule