parent
3b7ddce207
commit
ec3c9832de
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@ -371,7 +371,7 @@ public:
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FileLine* driverFileLine(size_t idx) const { return m_driverData.at(idx).m_flp; }
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FileLine* driverFileLine(size_t idx) const { return m_driverData.at(idx).m_flp; }
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DfgVertex* driverAt(size_t idx) {
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DfgVertex* driverAt(size_t idx) const {
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const size_t n = nInputs();
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const size_t n = nInputs();
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for (size_t i = 0; i < n; ++i) {
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for (size_t i = 0; i < n; ++i) {
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if (m_driverData[i].m_lo == idx) return inputp(i);
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if (m_driverData[i].m_lo == idx) return inputp(i);
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@ -379,13 +379,6 @@ public:
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return nullptr;
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return nullptr;
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}
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}
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const DfgVertex* driverAt(size_t idx) const {
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for (const DriverData& dd : m_driverData) {
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if (dd.m_lo == idx) return inputp(idx);
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}
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return nullptr;
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}
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// If drives the whole result explicitly (not through defaultp), this is
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// If drives the whole result explicitly (not through defaultp), this is
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// the actual driver this DfgVertexSplice can be replaced with.
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// the actual driver this DfgVertexSplice can be replaced with.
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DfgVertex* wholep() {
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DfgVertex* wholep() {
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@ -261,4 +261,14 @@ module t (
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`signal(PACKED_0_LSB, 1);
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`signal(PACKED_0_LSB, 1);
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assign PACKED_0_LSB = packed_0_lsb;
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assign PACKED_0_LSB = packed_0_lsb;
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// verilator lint_off UNOPTFLAT
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logic array_5 [0:6];
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// Unconnected d[0:3]
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assign array_5[4] = array_5[0] ? array_5[0] : array_5[1];
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assign array_5[5] = array_5[2] ? array_5[2] : array_5[3];
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assign array_5[6] = array_5[4] ? array_5[4] : array_5[5];
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`signal(ARRAY_5, 1);
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assign ARRAY_5 = array_5[6];
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// verilator lint_on
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endmodule
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endmodule
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