mirror of
https://github.com/verilator/verilator.git
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+3
-3
@@ -1718,7 +1718,7 @@ class SvaNfaLowering final {
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AstNodeExpr* srcSigp = c.vtx[fromIdx]->datap()->stateSigp->cloneTreePure(false);
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srcSigp = andCond(c.flp, srcSigp, te.m_condp);
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if (c.disableExprp && !c.snapshotVarp) {
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if (c.disableExprp) {
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AstNodeExpr* const notDisp
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= new AstLogNot{c.flp, c.disableExprp->cloneTreePure(false)};
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srcSigp = new AstLogAnd{c.flp, srcSigp, notDisp};
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@@ -1770,7 +1770,7 @@ class SvaNfaLowering final {
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"Delay-ring incoming source missing stateSig");
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AstNodeExpr* contribp = c.vtx[fi]->datap()->stateSigp->cloneTreePure(false);
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contribp = andCond(c.flp, contribp, tep->m_condp);
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if (c.disableExprp && !c.snapshotVarp) {
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if (c.disableExprp) {
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AstNodeExpr* const notDisp
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= new AstLogNot{c.flp, c.disableExprp->cloneTreePure(false)};
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contribp = new AstLogAnd{c.flp, contribp, notDisp};
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@@ -1805,7 +1805,7 @@ class SvaNfaLowering final {
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if (vtxp->m_delayRingClearCondp) {
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clearCondp = sampled(vtxp->m_delayRingClearCondp->cloneTreePure(false));
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}
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if (c.disableExprp && !c.snapshotVarp) {
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if (c.disableExprp) {
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clearCondp = orExprs(c.flp, clearCondp, c.disableExprp->cloneTreePure(false));
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}
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AstNodeExpr* guardp = nullptr;
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