Tests

test_regress/t/t_interface2.v

@@ -22,7 +22,7 @@ module t (/*AUTOARG*/
    counter    c1 (.clkm(clk),
 		  .c_data(c1_data),
 		  .i_value(4'h1));
-   counter    c2 (.clkm(clk),
+   counter2   c2 (.clkm(clk),
 		  .c_data(c2_data),
 		  .i_value(4'h2));
 
@@ -66,3 +66,16 @@ module counter
 	c_data.value <= c_data.value + 1;
    end
 endmodule : counter
+
+module counter2(clkm, c_data, i_value);
+   input clkm;
+   counter_io c_data;
+   input logic [3:0] i_value;
+
+   always @ (posedge clkm) begin
+      if (c_data.reset)
+	c_data.value <= i_value;
+      else
+	c_data.value <= c_data.value + 1;
+   end
+endmodule : counter2

test_regress/t/t_interface_top.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 $Self->{vlt} and $Self->unsupported("Verilator unsupported, bug102");
 
 compile (
-    v_flags => ["--lint-only"]
+    verilator_flags2 => ["--lint-only"]
     );
 
 ok(1);

test_regress/t/t_interface_top.v

@@ -10,13 +10,12 @@ interface counter_io;
    modport core_side (output reset, input value);
 endinterface
 
-module t (/*AUTOARG*/
-   // Inputs
-   clk,
+module t
+  (// Inputs
+   input clk,
    counter_io.counter_side c_data
    );
 
-   input clk;
    integer cyc=1;
 
 endmodule