Fix fault on defparam with UNSUPPORTED ignored (#5450).

Changes

@@ -42,7 +42,7 @@ Verilator 5.029 devel
 * Fix clearing trigger of events with no sensitivity trees (#5426). [Arkadiusz Kozdra, Antmicro Ltd.]
 * Fix driving clocking block in reactive region (#5430). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix associative array next/prev/first/last mis-propagating constants (#5435). [Ethan Sifferman]
-
+* Fix fault on defparam with UNSUPPORTED ignored (#5450). [Luiza de Melo]
 
 
 Verilator 5.028 2024-08-21

src/verilog.y

@@ -3182,12 +3182,14 @@ type_assignment<varp>:          // ==IEEE: type_assignment
 
 list_of_type_assignments<varp>:         // ==IEEE: list_of_type_assignments
                 type_assignment                         { $$ = $1; }
-        |       list_of_type_assignments ',' type_assignment    { $$ = $1->addNext($3); }
+        |       list_of_type_assignments ',' type_assignment
+                        { $$ = addNextNull($1, $3); }
         ;
 
 list_of_defparam_assignments<nodep>:    //== IEEE: list_of_defparam_assignments
                 defparam_assignment                     { $$ = $1; }
-        |       list_of_defparam_assignments ',' defparam_assignment    { $$ = $1->addNext($3); }
+        |       list_of_defparam_assignments ',' defparam_assignment
+                        { $$ = addNextNull($1, $3); }
         ;
 
 defparam_assignment<nodep>:     // ==IEEE: defparam_assignment
@@ -5615,7 +5617,7 @@ gateXorPinList<nodeExprp>:
         ;
 gateUnsupPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
-        |       gateUnsupPinList ',' gatePinExpr        { $$ = $1->addNext($3); }
+        |       gateUnsupPinList ',' gatePinExpr        { $$ = addNextNull($1, $3); }
         ;
 
 gatePinExpr<nodeExprp>:

test_regress/t/t_gen_defparam_bad.out

@@ -0,0 +1,11 @@
+%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:9:12: Unsupported: defparam with no dot
+    9 |      id_15 = id_14;
+      |            ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:18: Unsupported: defparam with no dot
+   11 |    defparam id_8 = 1, id_9 = 1;
+      |                  ^
+%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:28: Unsupported: defparam with no dot
+   11 |    defparam id_8 = 1, id_9 = 1;
+      |                            ^
+%Error: Exiting due to

test_regress/t/t_gen_defparam_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_gen_defparam_bad.v

@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+   defparam id_13.id_14 = -id_13,
+     id_15 = id_14;
+
+   defparam id_8 = 1, id_9 = 1;
+endmodule